^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * under the terms and conditions of the GNU General Public License,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * version 2, as published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed in the hope it will be useful, but WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef __SOC_ROCKCHIP_SCPI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define __SOC_ROCKCHIP_SCPI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifdef CONFIG_RK3368_SCPI_PROTOCOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct scpi_opp_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 volt_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct scpi_opp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct scpi_opp_entry *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 latency; /* in usecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long scpi_clk_get_val(u16 clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int scpi_clk_set_val(u16 clk_id, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int scpi_dvfs_get_idx(u8 domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int scpi_dvfs_set_idx(u8 domain, u8 idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct scpi_opp *scpi_dvfs_get_opps(u8 domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int scpi_get_sensor(char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int scpi_get_sensor_value(u16 sensor, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int scpi_sys_set_jtagmux_on_off(u32 en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int scpi_sys_set_mcu_state_suspend(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int scpi_sys_set_mcu_state_resume(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int scpi_ddr_dclk_mode(u32 dclk_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 addr_mcu_el3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int scpi_ddr_send_timing(u32 *p, u32 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int scpi_ddr_round_rate(u32 m_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int scpi_ddr_set_auto_self_refresh(u32 en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int scpi_ddr_get_clk_rate(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int scpi_thermal_get_temperature(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int scpi_thermal_set_clk_cycle(u32 cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static inline unsigned long scpi_clk_get_val(u16 clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline int scpi_clk_set_val(u16 clk_id, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static inline int scpi_dvfs_get_idx(u8 domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline int scpi_dvfs_set_idx(u8 domain, u8 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static inline struct scpi_opp *scpi_dvfs_get_opps(u8 domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return ERR_PTR(-EPERM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static inline int scpi_get_sensor(char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static inline int scpi_get_sensor_value(u16 sensor, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline int scpi_sys_set_jtagmux_on_off(u32 en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline int scpi_sys_set_mcu_state_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline int scpi_sys_set_mcu_state_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline int scpi_ddr_dclk_mode(u32 dclk_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 addr_mcu_el3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static inline int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static inline int scpi_ddr_send_timing(u32 *p, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline int scpi_ddr_round_rate(u32 m_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static inline int scpi_ddr_set_auto_self_refresh(u32 en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline int scpi_ddr_get_clk_rate(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline int scpi_thermal_get_temperature(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline int scpi_thermal_set_clk_cycle(u32 cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags