^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2022 Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef __SOC_ROCKCHIP_DVBM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define __SOC_ROCKCHIP_DVBM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/dma-buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) enum dvbm_port_dir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) DVBM_ISP_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) DVBM_VEPU_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum dvbm_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) DVBM_ISP_CMD_BASE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) DVBM_ISP_SET_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) DVBM_ISP_FRM_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) DVBM_ISP_FRM_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) DVBM_ISP_FRM_QUARTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) DVBM_ISP_FRM_HALF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) DVBM_ISP_FRM_THREE_QUARTERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) DVBM_ISP_CMD_BUTT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DVBM_VEPU_CMD_BASE = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DVBM_VEPU_SET_RESYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DVBM_VEPU_SET_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DVBM_VEPU_GET_ADR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DVBM_VEPU_GET_FRAME_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DVBM_VEPU_DUMP_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DVBM_VEPU_CMD_BUTT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enum isp_frame_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ISP_FRAME_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ISP_FRAME_ONE_QUARTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ISP_FRAME_HALF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ISP_FRAME_THREE_QUARTERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ISP_FRAME_FINISH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum dvbm_cb_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DVBM_ISP_EVENT_BASE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DVBM_ISP_EVENT_BUTT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DVBM_VEPU_EVENT_BASE = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DVBM_VEPU_NOTIFY_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DVBM_VEPU_NOTIFY_DUMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DVBM_VEPU_REQ_CONNECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DVBM_VEPU_NOTIFY_FRM_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DVBM_VEPU_NOTIFY_FRM_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DVBM_VEPU_NOTIFY_FRM_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DVBM_VEPU_EVENT_BUTT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct dvbm_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum dvbm_port_dir dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 linked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct dvbm_isp_cfg_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct dmabuf *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 ybuf_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 ybuf_bot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 ybuf_lstd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 ybuf_fstd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 cbuf_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 cbuf_bot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 cbuf_lstd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 cbuf_fstd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct dvbm_isp_frm_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) s32 frm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 ybuf_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 cbuf_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct dvbm_isp_frm_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 frame_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 line_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 wrap_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 max_line_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct dvbm_addr_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 ybuf_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 ybuf_bot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 ybuf_sadr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 cbuf_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 cbuf_bot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 cbuf_sadr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 frame_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 line_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 overflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct dvbm_vepu_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 auto_resyn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 ignore_vepu_cnct_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 start_point_after_vepu_cnct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) typedef int (*dvbm_callback)(void *ctx, enum dvbm_cb_event event, void *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct dvbm_cb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dvbm_callback cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #if IS_ENABLED(CONFIG_ROCKCHIP_DVBM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct dvbm_port *rk_dvbm_get_port(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum dvbm_port_dir dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int rk_dvbm_put(struct dvbm_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int rk_dvbm_link(struct dvbm_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int rk_dvbm_unlink(struct dvbm_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int rk_dvbm_set_cb(struct dvbm_port *port, struct dvbm_cb *cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int rk_dvbm_ctrl(struct dvbm_port *port, enum dvbm_cmd cmd, void *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline struct dvbm_port *rk_dvbm_get_port(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) enum dvbm_port_dir dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static inline int rk_dvbm_put(struct dvbm_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline int rk_dvbm_link(struct dvbm_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static inline int rk_dvbm_unlink(struct dvbm_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static inline int rk_dvbm_set_cb(struct dvbm_port *port, struct dvbm_cb *cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline int rk_dvbm_ctrl(struct dvbm_port *port, enum dvbm_cmd cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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