^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * licenses. You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * COPYING in the main directory of this source tree, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * OpenIB.org BSD license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Redistribution and use in source and binary forms, with or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * without modification, are permitted provided that the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * - Redistributions of source code must retain the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * - Redistributions in binary form must reproduce the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * copyright notice, this list of conditions and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * disclaimer in the documentation and/or other materials
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifndef SOC_NPS_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SOC_NPS_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NPS_IPI_IRQ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NPS_HOST_REG_BASE 0xF6000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NPS_MSU_BLKID 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #ifndef AUX_IENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AUX_IENABLE 0x40c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CTOP_AUX_IACK (0xFFFFF800 + 0x088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* In order to increase compilation test coverage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #ifdef CONFIG_ARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static inline void nps_ack_gic(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __asm__ __volatile__ (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) " .word %0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) : "i"(CTOP_INST_RSPI_GIC_0_R12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static inline void nps_ack_gic(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define write_aux_reg(r, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define read_aux_reg(r) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* CPU global ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct global_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifdef CONFIG_EZNPS_MTM_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 __reserved:20, cluster:4, core:4, thread:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 __reserved:24, cluster:4, core:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Convert logical to physical CPU IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Now quad of logical clusters id's are adjacent physically,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * and not like the id's physically came with each cluster.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Below table is 4x4 mesh of core clusters as it layout on chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Cluster ids are in format: logical (physical)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * ----------------- ------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * 3 | 5 (3) 7 (7) | | 13 (11) 15 (15)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * 2 | 4 (2) 6 (6) | | 12 (10) 14 (14)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * ----------------- ------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * 1 | 1 (1) 3 (5) | | 9 (9) 11 (13)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * 0 | 0 (0) 2 (4) | | 8 (8) 10 (12)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * ----------------- ------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * 0 1 2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline int nps_cluster_logic_to_phys(int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #ifdef __arc__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) " mov r3,%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) " .short %1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) " .word %2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) " mov %0,r3\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) : "+r"(cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) : "r3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define NPS_CPU_TO_CLUSTER_NUM(cpu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ({ struct global_id gid; gid.value = cpu; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) nps_cluster_logic_to_phys(gid.cluster); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct nps_host_reg_address {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 base:8, cl_x:4, cl_y:4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) blkid:6, reg:8, __reserved:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct nps_host_reg_address_non_cl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 base:7, blkid:11, reg:12, __reserved:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct nps_host_reg_address_non_cl reg_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) reg_address.value = NPS_HOST_REG_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) reg_address.blkid = blkid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) reg_address.reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return (void *)reg_address.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct nps_host_reg_address reg_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) reg_address.value = NPS_HOST_REG_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) reg_address.cl_x = (cl >> 2) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) reg_address.cl_y = cl & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) reg_address.blkid = blkid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) reg_address.reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return (void *)reg_address.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif /* SOC_NPS_COMMON_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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