^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Microsemi Ocelot Switch driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019 Microsemi Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _OCELOT_VCAP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _OCELOT_VCAP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <soc/mscc/ocelot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* =================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * VCAP Common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * =================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) VCAP_ES0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) VCAP_IS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) VCAP_IS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) __VCAP_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OCELOT_NUM_VCAP_BLOCKS __VCAP_COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct vcap_props {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u16 tg_width; /* Type-group width (in bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u16 sw_count; /* Sub word count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u16 entry_count; /* Entry count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u16 entry_words; /* Number of entry words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u16 entry_width; /* Entry width (in bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u16 action_count; /* Action count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u16 action_words; /* Number of action words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u16 action_width; /* Action width (in bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u16 action_type_width; /* Action type width (in bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u16 width; /* Action type width (in bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u16 count; /* Action type sub word count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) } action_table[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u16 counter_words; /* Number of counter words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u16 counter_width; /* Counter width (in bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum ocelot_target target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) const struct vcap_field *keys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) const struct vcap_field *actions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* VCAP Type-Group values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VCAP_TG_NONE 0 /* Entry is invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VCAP_TG_FULL 1 /* Full entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VCAP_TG_HALF 2 /* Half entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VCAP_TG_QUARTER 3 /* Quarter entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD(x) (((x) << 22) & GENMASK(24, 22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_M GENMASK(24, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_X(x) (((x) & GENMASK(24, 22)) >> 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VCAP_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VCAP_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VCAP_CORE_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR(x) (((x) << 3) & GENMASK(18, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_M GENMASK(18, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_X(x) (((x) & GENMASK(18, 3)) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VCAP_CORE_UPDATE_CTRL_CLEAR_CACHE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VCAP_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VCAP_CORE_MV_CFG_MV_NUM_POS(x) (((x) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VCAP_CORE_MV_CFG_MV_NUM_POS_M GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VCAP_CORE_MV_CFG_MV_NUM_POS_X(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VCAP_CORE_MV_CFG_MV_SIZE(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VCAP_CORE_MV_CFG_MV_SIZE_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VCAP_CACHE_ENTRY_DAT_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VCAP_CACHE_MASK_DAT_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define VCAP_CACHE_ACTION_DAT_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VCAP_CACHE_CNT_DAT_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TCAM_BIST_CTRL_TCAM_BIST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TCAM_BIST_CTRL_TCAM_INIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TCAM_BIST_CFG_TCAM_BIST_SOE_ENA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TCAM_BIST_CFG_TCAM_HCG_DIS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TCAM_BIST_CFG_TCAM_CG_DIS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TCAM_BIST_CFG_TCAM_BIAS(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TCAM_BIST_CFG_TCAM_BIAS_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TCAM_BIST_STAT_BIST_RT_ERR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TCAM_BIST_STAT_BIST_PENC_ERR BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TCAM_BIST_STAT_BIST_COMP_ERR BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TCAM_BIST_STAT_BIST_ADDR_ERR BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TCAM_BIST_STAT_BIST_BL1E_ERR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TCAM_BIST_STAT_BIST_BL1_ERR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TCAM_BIST_STAT_BIST_BL0E_ERR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TCAM_BIST_STAT_BIST_BL0_ERR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TCAM_BIST_STAT_BIST_PH1_ERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TCAM_BIST_STAT_BIST_PH0_ERR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TCAM_BIST_STAT_BIST_PV1_ERR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TCAM_BIST_STAT_BIST_PV0_ERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TCAM_BIST_STAT_BIST_RUN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TCAM_BIST_STAT_BIST_ERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TCAM_BIST_STAT_BIST_BUSY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TCAM_BIST_STAT_TCAM_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* =================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * VCAP IS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * =================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* IS2 half key types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IS2_TYPE_ETYPE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IS2_TYPE_LLC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IS2_TYPE_SNAP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IS2_TYPE_ARP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IS2_TYPE_IP_UDP_TCP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IS2_TYPE_IP_OTHER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IS2_TYPE_IPV6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IS2_TYPE_OAM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IS2_TYPE_SMAC_SIP6 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IS2_TYPE_ANY 100 /* Pseudo type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* IS2 half key type mask for matching any IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IS2_TYPE_MASK_IP_ANY 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) IS2_ACTION_TYPE_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) IS2_ACTION_TYPE_SMAC_SIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) IS2_ACTION_TYPE_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* IS2 MASK_MODE values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IS2_ACT_MASK_MODE_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IS2_ACT_MASK_MODE_FILTER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IS2_ACT_MASK_MODE_POLICY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IS2_ACT_MASK_MODE_REDIR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* IS2 REW_OP values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IS2_ACT_REW_OP_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IS2_ACT_REW_OP_PTP_ONE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IS2_ACT_REW_OP_PTP_TWO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IS2_ACT_REW_OP_SPECIAL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IS2_ACT_REW_OP_PTP_ORG 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1 (IS2_ACT_REW_OP_PTP_ONE | (1 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2 (IS2_ACT_REW_OP_PTP_ONE | (2 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY (IS2_ACT_REW_OP_PTP_ONE | (1 << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define VCAP_PORT_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* IS2 quarter key - SMAC_SIP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IS2_QKO_IGR_PORT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IS2_QKL_IGR_PORT VCAP_PORT_WIDTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IS2_QKO_L2_SMAC (IS2_QKO_IGR_PORT + IS2_QKL_IGR_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IS2_QKL_L2_SMAC 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IS2_QKO_L3_IP4_SIP (IS2_QKO_L2_SMAC + IS2_QKL_L2_SMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IS2_QKL_L3_IP4_SIP 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) enum vcap_is2_half_key_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) VCAP_IS2_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) VCAP_IS2_HK_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) VCAP_IS2_HK_PAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) VCAP_IS2_HK_RSV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) VCAP_IS2_HK_IGR_PORT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) VCAP_IS2_HK_RSV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) VCAP_IS2_HK_HOST_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) VCAP_IS2_HK_L2_MC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) VCAP_IS2_HK_L2_BC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) VCAP_IS2_HK_VLAN_TAGGED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) VCAP_IS2_HK_VID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) VCAP_IS2_HK_DEI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) VCAP_IS2_HK_PCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) VCAP_IS2_HK_L2_DMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) VCAP_IS2_HK_L2_SMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* MAC_ETYPE (TYPE=000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) VCAP_IS2_HK_MAC_ETYPE_ETYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* MAC_LLC (TYPE=001) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) VCAP_IS2_HK_MAC_LLC_DMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) VCAP_IS2_HK_MAC_LLC_SMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) VCAP_IS2_HK_MAC_LLC_L2_LLC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* MAC_SNAP (TYPE=010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) VCAP_IS2_HK_MAC_SNAP_SMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) VCAP_IS2_HK_MAC_SNAP_DMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) VCAP_IS2_HK_MAC_SNAP_L2_SNAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* MAC_ARP (TYPE=011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) VCAP_IS2_HK_MAC_ARP_SMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) VCAP_IS2_HK_MAC_ARP_LEN_OK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) VCAP_IS2_HK_MAC_ARP_TARGET_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) VCAP_IS2_HK_MAC_ARP_SENDER_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) VCAP_IS2_HK_MAC_ARP_OPCODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* IP4_TCP_UDP / IP4_OTHER common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) VCAP_IS2_HK_IP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) VCAP_IS2_HK_L3_FRAGMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) VCAP_IS2_HK_L3_FRAG_OFS_GT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) VCAP_IS2_HK_L3_OPTIONS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) VCAP_IS2_HK_IP4_L3_TTL_GT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) VCAP_IS2_HK_L3_TOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) VCAP_IS2_HK_L3_IP4_DIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) VCAP_IS2_HK_L3_IP4_SIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) VCAP_IS2_HK_DIP_EQ_SIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* IP4_TCP_UDP (TYPE=100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) VCAP_IS2_HK_TCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) VCAP_IS2_HK_L4_SPORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) VCAP_IS2_HK_L4_DPORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) VCAP_IS2_HK_L4_RNG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) VCAP_IS2_HK_L4_SPORT_EQ_DPORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) VCAP_IS2_HK_L4_SEQUENCE_EQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) VCAP_IS2_HK_L4_URG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) VCAP_IS2_HK_L4_ACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) VCAP_IS2_HK_L4_PSH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) VCAP_IS2_HK_L4_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) VCAP_IS2_HK_L4_SYN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) VCAP_IS2_HK_L4_FIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) VCAP_IS2_HK_L4_1588_DOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) VCAP_IS2_HK_L4_1588_VER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* IP4_OTHER (TYPE=101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) VCAP_IS2_HK_IP4_L3_PROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) VCAP_IS2_HK_L3_PAYLOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* IP6_STD (TYPE=110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) VCAP_IS2_HK_IP6_L3_TTL_GT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) VCAP_IS2_HK_IP6_L3_PROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) VCAP_IS2_HK_L3_IP6_SIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* OAM (TYPE=111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) VCAP_IS2_HK_OAM_MEL_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) VCAP_IS2_HK_OAM_VER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) VCAP_IS2_HK_OAM_OPCODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) VCAP_IS2_HK_OAM_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) VCAP_IS2_HK_OAM_MEPID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) VCAP_IS2_HK_OAM_CCM_CNTS_EQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) VCAP_IS2_HK_OAM_IS_Y1731,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct vcap_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) enum vcap_is2_action_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) VCAP_IS2_ACT_HIT_ME_ONCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) VCAP_IS2_ACT_CPU_COPY_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) VCAP_IS2_ACT_CPU_QU_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) VCAP_IS2_ACT_MASK_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) VCAP_IS2_ACT_MIRROR_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) VCAP_IS2_ACT_LRN_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) VCAP_IS2_ACT_POLICE_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) VCAP_IS2_ACT_POLICE_IDX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) VCAP_IS2_ACT_POLICE_VCAP_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) VCAP_IS2_ACT_PORT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) VCAP_IS2_ACT_REW_OP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) VCAP_IS2_ACT_SMAC_REPLACE_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) VCAP_IS2_ACT_RSV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) VCAP_IS2_ACT_ACL_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) VCAP_IS2_ACT_HIT_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* =================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * VCAP IS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * =================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* IS1 half key types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IS1_TYPE_S1_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IS1_TYPE_S1_5TUPLE_IP4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* IS1 full key types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IS1_TYPE_S1_NORMAL_IP6 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IS1_TYPE_S1_7TUPLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IS2_TYPE_S1_5TUPLE_IP6 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) IS1_ACTION_TYPE_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) IS1_ACTION_TYPE_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) enum vcap_is1_half_key_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) VCAP_IS1_HK_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) VCAP_IS1_HK_LOOKUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) VCAP_IS1_HK_IGR_PORT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) VCAP_IS1_HK_RSV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) VCAP_IS1_HK_OAM_Y1731,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) VCAP_IS1_HK_L2_MC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) VCAP_IS1_HK_L2_BC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) VCAP_IS1_HK_IP_MC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) VCAP_IS1_HK_VLAN_TAGGED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) VCAP_IS1_HK_VLAN_DBL_TAGGED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) VCAP_IS1_HK_TPID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) VCAP_IS1_HK_VID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) VCAP_IS1_HK_DEI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) VCAP_IS1_HK_PCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Specific Fields for IS1 Half Key S1_NORMAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) VCAP_IS1_HK_L2_SMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) VCAP_IS1_HK_ETYPE_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) VCAP_IS1_HK_ETYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) VCAP_IS1_HK_IP_SNAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) VCAP_IS1_HK_IP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) VCAP_IS1_HK_L3_FRAGMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) VCAP_IS1_HK_L3_FRAG_OFS_GT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) VCAP_IS1_HK_L3_OPTIONS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) VCAP_IS1_HK_L3_DSCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) VCAP_IS1_HK_L3_IP4_SIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) VCAP_IS1_HK_TCP_UDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) VCAP_IS1_HK_TCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) VCAP_IS1_HK_L4_SPORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) VCAP_IS1_HK_L4_RNG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) VCAP_IS1_HK_IP4_INNER_TPID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) VCAP_IS1_HK_IP4_INNER_VID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) VCAP_IS1_HK_IP4_INNER_DEI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) VCAP_IS1_HK_IP4_INNER_PCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) VCAP_IS1_HK_IP4_IP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) VCAP_IS1_HK_IP4_L3_FRAGMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) VCAP_IS1_HK_IP4_L3_OPTIONS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) VCAP_IS1_HK_IP4_L3_DSCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) VCAP_IS1_HK_IP4_L3_IP4_DIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) VCAP_IS1_HK_IP4_L3_IP4_SIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) VCAP_IS1_HK_IP4_L3_PROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) VCAP_IS1_HK_IP4_TCP_UDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) VCAP_IS1_HK_IP4_TCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) VCAP_IS1_HK_IP4_L4_RNG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) enum vcap_is1_action_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) VCAP_IS1_ACT_DSCP_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) VCAP_IS1_ACT_DSCP_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) VCAP_IS1_ACT_QOS_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) VCAP_IS1_ACT_QOS_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) VCAP_IS1_ACT_DP_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) VCAP_IS1_ACT_DP_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) VCAP_IS1_ACT_PAG_OVERRIDE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) VCAP_IS1_ACT_PAG_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) VCAP_IS1_ACT_RSV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) VCAP_IS1_ACT_VID_REPLACE_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) VCAP_IS1_ACT_VID_ADD_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) VCAP_IS1_ACT_FID_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) VCAP_IS1_ACT_FID_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) VCAP_IS1_ACT_PCP_DEI_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) VCAP_IS1_ACT_PCP_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) VCAP_IS1_ACT_DEI_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) VCAP_IS1_ACT_VLAN_POP_CNT_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) VCAP_IS1_ACT_VLAN_POP_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) VCAP_IS1_ACT_HIT_STICKY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* =================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * VCAP ES0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * =================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ES0_ACTION_TYPE_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ES0_ACTION_TYPE_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) enum vcap_es0_key_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) VCAP_ES0_EGR_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) VCAP_ES0_IGR_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) VCAP_ES0_RSV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) VCAP_ES0_L2_MC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) VCAP_ES0_L2_BC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) VCAP_ES0_VID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) VCAP_ES0_DP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) VCAP_ES0_PCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) enum vcap_es0_action_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) VCAP_ES0_ACT_PUSH_OUTER_TAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) VCAP_ES0_ACT_PUSH_INNER_TAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) VCAP_ES0_ACT_TAG_A_TPID_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) VCAP_ES0_ACT_TAG_A_VID_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) VCAP_ES0_ACT_TAG_A_PCP_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) VCAP_ES0_ACT_TAG_A_DEI_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) VCAP_ES0_ACT_TAG_B_TPID_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) VCAP_ES0_ACT_TAG_B_VID_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) VCAP_ES0_ACT_TAG_B_PCP_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) VCAP_ES0_ACT_TAG_B_DEI_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) VCAP_ES0_ACT_VID_A_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) VCAP_ES0_ACT_PCP_A_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) VCAP_ES0_ACT_DEI_A_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) VCAP_ES0_ACT_VID_B_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) VCAP_ES0_ACT_PCP_B_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) VCAP_ES0_ACT_DEI_B_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) VCAP_ES0_ACT_RSV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) VCAP_ES0_ACT_HIT_STICKY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #endif /* _OCELOT_VCAP_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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