^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Microsemi Ocelot Switch driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017 Microsemi Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _MSCC_OCELOT_QSYS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _MSCC_OCELOT_QSYS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define QSYS_PORT_MODE_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define QSYS_EEE_CFG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define QSYS_SW_STATUS_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define QSYS_QMAP_GSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define QSYS_QMAP_SE_BASE_M GENMASK(12, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define QSYS_QMAP_SE_IDX_SEL_M GENMASK(4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define QSYS_QMAP_SE_IDX_SEL_X(x) (((x) & GENMASK(4, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define QSYS_QMAP_SE_INP_SEL(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define QSYS_QMAP_SE_INP_SEL_M GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define QSYS_ISDX_SGRP_GSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define QSYS_TIMED_FRAME_ENTRY_GSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x) (((x) << 9) & GENMASK(18, 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M GENMASK(18, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_X(x) (((x) & GENMASK(18, 9)) >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define QSYS_TFRM_MISC_TIMED_CANCEL_1SHOT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define QSYS_TFRM_MISC_TIMED_SLOT_MODE_MC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x) ((x) & GENMASK(6, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define QSYS_RED_PROFILE_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define QSYS_RED_PROFILE_WM_RED_LOW(x) (((x) << 8) & GENMASK(15, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define QSYS_RED_PROFILE_WM_RED_LOW_M GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define QSYS_RED_PROFILE_WM_RED_LOW_X(x) (((x) & GENMASK(15, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define QSYS_RED_PROFILE_WM_RED_HIGH(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define QSYS_RED_PROFILE_WM_RED_HIGH_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define QSYS_RES_CFG_GSZ 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define QSYS_RES_STAT_GSZ 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define QSYS_RES_STAT_INUSE(x) (((x) << 12) & GENMASK(23, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define QSYS_RES_STAT_INUSE_M GENMASK(23, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define QSYS_RES_STAT_INUSE_X(x) (((x) & GENMASK(23, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define QSYS_RES_STAT_MAXUSE(x) ((x) & GENMASK(11, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define QSYS_RES_STAT_MAXUSE_M GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define QSYS_EVENTS_CORE_EV_FDC(x) (((x) << 2) & GENMASK(4, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define QSYS_EVENTS_CORE_EV_FDC_M GENMASK(4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define QSYS_EVENTS_CORE_EV_FDC_X(x) (((x) & GENMASK(4, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define QSYS_EVENTS_CORE_EV_FRD(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define QSYS_EVENTS_CORE_EV_FRD_M GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define QSYS_QMAXSDU_CFG_0_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define QSYS_QMAXSDU_CFG_1_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define QSYS_QMAXSDU_CFG_2_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define QSYS_QMAXSDU_CFG_3_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define QSYS_QMAXSDU_CFG_4_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define QSYS_QMAXSDU_CFG_5_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define QSYS_QMAXSDU_CFG_6_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define QSYS_QMAXSDU_CFG_7_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define QSYS_PREEMPTION_CFG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define QSYS_PREEMPTION_CFG_P_QUEUES(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define QSYS_PREEMPTION_CFG_P_QUEUES_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(x) (((x) << 8) & GENMASK(9, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(x) (((x) & GENMASK(9, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define QSYS_PREEMPTION_CFG_STRICT_IPG(x) (((x) << 12) & GENMASK(13, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define QSYS_PREEMPTION_CFG_STRICT_IPG_M GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define QSYS_PREEMPTION_CFG_STRICT_IPG_X(x) (((x) & GENMASK(13, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE(x) (((x) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_M GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_X(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define QSYS_CIR_CFG_GSZ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define QSYS_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define QSYS_CIR_CFG_CIR_RATE_M GENMASK(20, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define QSYS_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define QSYS_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define QSYS_CIR_CFG_CIR_BURST_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define QSYS_EIR_CFG_GSZ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define QSYS_EIR_CFG_EIR_RATE(x) (((x) << 7) & GENMASK(21, 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define QSYS_EIR_CFG_EIR_RATE_M GENMASK(21, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define QSYS_EIR_CFG_EIR_RATE_X(x) (((x) & GENMASK(21, 7)) >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define QSYS_EIR_CFG_EIR_BURST(x) (((x) << 1) & GENMASK(6, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define QSYS_EIR_CFG_EIR_BURST_M GENMASK(6, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define QSYS_EIR_CFG_EIR_BURST_X(x) (((x) & GENMASK(6, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define QSYS_EIR_CFG_EIR_MARK_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define QSYS_SE_CFG_GSZ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define QSYS_SE_CFG_SE_DWRR_CNT(x) (((x) << 6) & GENMASK(9, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define QSYS_SE_CFG_SE_DWRR_CNT_M GENMASK(9, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define QSYS_SE_CFG_SE_DWRR_CNT_X(x) (((x) & GENMASK(9, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define QSYS_SE_CFG_SE_RR_ENA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define QSYS_SE_CFG_SE_AVB_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define QSYS_SE_CFG_SE_FRM_MODE(x) (((x) << 2) & GENMASK(3, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define QSYS_SE_CFG_SE_FRM_MODE_M GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define QSYS_SE_CFG_SE_FRM_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define QSYS_SE_CFG_SE_EXC_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define QSYS_SE_CFG_SE_EXC_FWD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define QSYS_SE_DWRR_CFG_GSZ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define QSYS_SE_DWRR_CFG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define QSYS_SE_CONNECT_GSZ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define QSYS_SE_CONNECT_SE_OUTP_IDX(x) (((x) << 17) & GENMASK(24, 17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define QSYS_SE_CONNECT_SE_OUTP_IDX_M GENMASK(24, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define QSYS_SE_CONNECT_SE_OUTP_IDX_X(x) (((x) & GENMASK(24, 17)) >> 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define QSYS_SE_CONNECT_SE_INP_IDX(x) (((x) << 9) & GENMASK(16, 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define QSYS_SE_CONNECT_SE_INP_IDX_M GENMASK(16, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define QSYS_SE_CONNECT_SE_INP_IDX_X(x) (((x) & GENMASK(16, 9)) >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define QSYS_SE_CONNECT_SE_OUTP_CON(x) (((x) << 5) & GENMASK(8, 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define QSYS_SE_CONNECT_SE_OUTP_CON_M GENMASK(8, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define QSYS_SE_CONNECT_SE_OUTP_CON_X(x) (((x) & GENMASK(8, 5)) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define QSYS_SE_CONNECT_SE_INP_CNT(x) (((x) << 1) & GENMASK(4, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define QSYS_SE_CONNECT_SE_INP_CNT_M GENMASK(4, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define QSYS_SE_CONNECT_SE_INP_CNT_X(x) (((x) & GENMASK(4, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define QSYS_SE_CONNECT_SE_TERMINAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define QSYS_SE_DLB_SENSE_GSZ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO(x) (((x) << 11) & GENMASK(13, 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_M GENMASK(13, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_X(x) (((x) & GENMASK(13, 11)) >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT(x) (((x) << 7) & GENMASK(10, 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_M GENMASK(10, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_X(x) (((x) & GENMASK(10, 7)) >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT(x) (((x) << 3) & GENMASK(6, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_M GENMASK(6, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_X(x) (((x) & GENMASK(6, 3)) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define QSYS_CIR_STATE_GSZ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define QSYS_CIR_STATE_CIR_LVL(x) (((x) << 4) & GENMASK(25, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define QSYS_CIR_STATE_CIR_LVL_M GENMASK(25, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define QSYS_CIR_STATE_CIR_LVL_X(x) (((x) & GENMASK(25, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define QSYS_CIR_STATE_SHP_TIME(x) ((x) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define QSYS_CIR_STATE_SHP_TIME_M GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define QSYS_EIR_STATE_GSZ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define QSYS_SE_STATE_GSZ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define QSYS_SE_STATE_SE_OUTP_LVL(x) (((x) << 1) & GENMASK(2, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define QSYS_SE_STATE_SE_OUTP_LVL_M GENMASK(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define QSYS_SE_STATE_SE_OUTP_LVL_X(x) (((x) & GENMASK(2, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define QSYS_SE_STATE_SE_WAS_YEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define QSYS_HSCH_MISC_CFG_SE_CONNECT_VLD BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define QSYS_HSCH_MISC_CFG_FRM_ADJ(x) (((x) << 3) & GENMASK(7, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define QSYS_HSCH_MISC_CFG_FRM_ADJ_M GENMASK(7, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define QSYS_HSCH_MISC_CFG_FRM_ADJ_X(x) (((x) & GENMASK(7, 3)) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define QSYS_HSCH_MISC_CFG_LEAK_DIS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define QSYS_HSCH_MISC_CFG_QSHP_EXC_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define QSYS_HSCH_MISC_CFG_PFC_BYP_UPD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define QSYS_TAG_CONFIG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define QSYS_TAG_CONFIG_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define QSYS_TAG_CONFIG_LINK_SPEED(x) (((x) << 4) & GENMASK(5, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define QSYS_TAG_CONFIG_LINK_SPEED_M GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define QSYS_TAG_CONFIG_LINK_SPEED_X(x) (((x) & GENMASK(5, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define QSYS_TAG_CONFIG_INIT_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define QSYS_TAG_CONFIG_INIT_GATE_STATE_M GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define QSYS_TAG_CONFIG_INIT_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(x) (((x) << 16) & GENMASK(23, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_X(x) (((x) & GENMASK(23, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define QSYS_PORT_MAX_SDU_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_M GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define QSYS_GCL_CFG_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define QSYS_GCL_CFG_REG_1_GATE_STATE_M GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define QSYS_GCL_CFG_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_M GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE(x) (((x) << 16) & GENMASK(23, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_M GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_X(x) (((x) & GENMASK(23, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define QSYS_GCL_STATUS_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define QSYS_GCL_STATUS_REG_1_GATE_STATE_M GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define QSYS_GCL_STATUS_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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