^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Microsemi Ocelot Switch driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017 Microsemi Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _MSCC_OCELOT_HSIO_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _MSCC_OCELOT_HSIO_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define HSIO_PLL5G_CFG0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define HSIO_PLL5G_CFG1 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define HSIO_PLL5G_CFG2 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define HSIO_PLL5G_CFG3 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define HSIO_PLL5G_CFG4 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HSIO_PLL5G_CFG5 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HSIO_PLL5G_CFG6 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HSIO_PLL5G_STATUS0 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HSIO_PLL5G_STATUS1 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HSIO_PLL5G_BIST_CFG0 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HSIO_PLL5G_BIST_CFG1 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HSIO_PLL5G_BIST_CFG2 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HSIO_PLL5G_BIST_STAT0 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HSIO_PLL5G_BIST_STAT1 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HSIO_RCOMP_CFG0 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HSIO_RCOMP_STATUS 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HSIO_SYNC_ETH_CFG 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HSIO_SYNC_ETH_PLL_CFG 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HSIO_S1G_DES_CFG 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HSIO_S1G_IB_CFG 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HSIO_S1G_OB_CFG 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HSIO_S1G_SER_CFG 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HSIO_S1G_COMMON_CFG 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HSIO_S1G_PLL_CFG 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HSIO_S1G_PLL_STATUS 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HSIO_S1G_DFT_CFG0 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HSIO_S1G_DFT_CFG1 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HSIO_S1G_DFT_CFG2 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HSIO_S1G_TP_CFG 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HSIO_S1G_RC_PLL_BIST_CFG 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HSIO_S1G_MISC_CFG 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HSIO_S1G_DFT_STATUS 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HSIO_S1G_MISC_STATUS 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HSIO_MCB_S1G_ADDR_CFG 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HSIO_S6G_DIG_CFG 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HSIO_S6G_DFT_CFG0 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HSIO_S6G_DFT_CFG1 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HSIO_S6G_DFT_CFG2 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HSIO_S6G_TP_CFG0 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HSIO_S6G_TP_CFG1 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HSIO_S6G_RC_PLL_BIST_CFG 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HSIO_S6G_MISC_CFG 0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HSIO_S6G_OB_ANEG_CFG 0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HSIO_S6G_DFT_STATUS 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HSIO_S6G_ERR_CNT 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HSIO_S6G_MISC_STATUS 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HSIO_S6G_DES_CFG 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HSIO_S6G_IB_CFG 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HSIO_S6G_IB_CFG1 0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HSIO_S6G_IB_CFG2 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HSIO_S6G_IB_CFG3 0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HSIO_S6G_IB_CFG4 0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HSIO_S6G_IB_CFG5 0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HSIO_S6G_OB_CFG 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HSIO_S6G_OB_CFG1 0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HSIO_S6G_SER_CFG 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HSIO_S6G_COMMON_CFG 0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HSIO_S6G_PLL_CFG 0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HSIO_S6G_ACJTAG_CFG 0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HSIO_S6G_GP_CFG 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HSIO_S6G_IB_STATUS0 0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HSIO_S6G_IB_STATUS1 0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HSIO_S6G_ACJTAG_STATUS 0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HSIO_S6G_PLL_STATUS 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HSIO_S6G_REVID 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HSIO_MCB_S6G_ADDR_CFG 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HSIO_HW_CFG 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HSIO_HW_QSGMII_CFG 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HSIO_HW_QSGMII_STAT 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HSIO_CLK_CFG 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HSIO_TEMP_SENSOR_CTRL 0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define HSIO_TEMP_SENSOR_CFG 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HSIO_TEMP_SENSOR_STAT 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M GENMASK(11, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x) (((x) & GENMASK(11, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HSIO_PLL5G_CFG1_ROT_SPEED BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HSIO_PLL5G_CFG1_ROT_DIR BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HSIO_PLL5G_CFG1_READBACK_DATA_SEL BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HSIO_PLL5G_CFG1_RC_ENABLE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M GENMASK(13, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HSIO_PLL5G_CFG1_RC_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HSIO_PLL5G_CFG1_QUARTER_RATE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HSIO_PLL5G_CFG1_PWD_TX BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HSIO_PLL5G_CFG1_PWD_RX BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HSIO_PLL5G_CFG1_HALF_RATE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HSIO_PLL5G_CFG1_FORCE_SET_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HSIO_PLL5G_CFG2_ENA_TEST_MODE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HSIO_PLL5G_CFG2_ENA_FBTESTOUT BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HSIO_PLL5G_CFG2_ENA_RCPLL BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HSIO_PLL5G_CFG2_ENA_CP2 BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1 BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HSIO_PLL5G_CFG2_AMPC_SEL(x) (((x) << 16) & GENMASK(23, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HSIO_PLL5G_CFG2_AMPC_SEL_M GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HSIO_PLL5G_CFG2_AMPC_SEL_X(x) (((x) & GENMASK(23, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HSIO_PLL5G_CFG2_PWD_AMPCTRL_N BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HSIO_PLL5G_CFG2_ENA_AMPCTRL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HSIO_PLL5G_CFG2_FRC_FSM_POR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HSIO_PLL5G_CFG2_DISABLE_FSM_POR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HSIO_PLL5G_CFG2_GAIN_TEST(x) (((x) << 5) & GENMASK(9, 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HSIO_PLL5G_CFG2_GAIN_TEST_M GENMASK(9, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HSIO_PLL5G_CFG2_GAIN_TEST_X(x) (((x) & GENMASK(9, 5)) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HSIO_PLL5G_CFG2_EN_RESET_OVERRUN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HSIO_PLL5G_CFG2_EN_RESET_LIM_DET BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HSIO_PLL5G_CFG2_DISABLE_FSM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HSIO_PLL5G_CFG2_ENA_GAIN_TEST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x) (((x) << 22) & GENMASK(23, 22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M GENMASK(23, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x) (((x) & GENMASK(23, 22)) >> 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HSIO_PLL5G_CFG3_TESTOUT_SEL(x) (((x) << 19) & GENMASK(21, 19))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HSIO_PLL5G_CFG3_TESTOUT_SEL_M GENMASK(21, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HSIO_PLL5G_CFG3_TESTOUT_SEL_X(x) (((x) & GENMASK(21, 19)) >> 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HSIO_PLL5G_CFG3_ENA_TEST_OUT BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HSIO_PLL5G_CFG3_SEL_FBDCLK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HSIO_PLL5G_CFG3_RST_FB_N BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HSIO_PLL5G_CFG3_FORCE_LO BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HSIO_PLL5G_CFG3_FORCE_HI BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HSIO_PLL5G_CFG3_FORCE_ENA BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HSIO_PLL5G_CFG3_FORCE_CP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HSIO_PLL5G_CFG3_FBDIVSEL(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HSIO_PLL5G_CFG3_FBDIVSEL_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define HSIO_PLL5G_CFG4_IB_CTRL(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HSIO_PLL5G_CFG4_IB_CTRL_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HSIO_PLL5G_CFG5_OB_CTRL(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HSIO_PLL5G_CFG5_OB_CTRL_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HSIO_PLL5G_CFG6_REFCLK_SEL(x) (((x) << 20) & GENMASK(22, 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define HSIO_PLL5G_CFG6_REFCLK_SEL_M GENMASK(22, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define HSIO_PLL5G_CFG6_REFCLK_SEL_X(x) (((x) & GENMASK(22, 20)) >> 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define HSIO_PLL5G_CFG6_REFCLK_SRC BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define HSIO_PLL5G_CFG6_POR_DEL_SEL(x) (((x) << 16) & GENMASK(17, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define HSIO_PLL5G_CFG6_POR_DEL_SEL_M GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define HSIO_PLL5G_CFG6_POR_DEL_SEL_X(x) (((x) & GENMASK(17, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define HSIO_PLL5G_CFG6_DIV125REF_SEL(x) (((x) << 8) & GENMASK(15, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define HSIO_PLL5G_CFG6_DIV125REF_SEL_M GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define HSIO_PLL5G_CFG6_DIV125REF_SEL_X(x) (((x) & GENMASK(15, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define HSIO_PLL5G_CFG6_ENA_REFCLKC2 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define HSIO_PLL5G_CFG6_ENA_FBCLKC2 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define HSIO_PLL5G_STATUS0_RANGE_LIM BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define HSIO_PLL5G_STATUS0_CALIBRATION_ERR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define HSIO_PLL5G_STATUS0_CALIBRATION_DONE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define HSIO_PLL5G_STATUS0_READBACK_DATA(x) (((x) << 1) & GENMASK(8, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define HSIO_PLL5G_STATUS0_READBACK_DATA_M GENMASK(8, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define HSIO_PLL5G_STATUS0_READBACK_DATA_X(x) (((x) & GENMASK(8, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define HSIO_PLL5G_STATUS0_LOCK_STATUS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define HSIO_PLL5G_STATUS1_SIG_DEL(x) (((x) << 21) & GENMASK(28, 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define HSIO_PLL5G_STATUS1_SIG_DEL_M GENMASK(28, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define HSIO_PLL5G_STATUS1_SIG_DEL_X(x) (((x) & GENMASK(28, 21)) >> 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define HSIO_PLL5G_STATUS1_GAIN_STAT(x) (((x) << 16) & GENMASK(20, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define HSIO_PLL5G_STATUS1_GAIN_STAT_M GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define HSIO_PLL5G_STATUS1_GAIN_STAT_X(x) (((x) & GENMASK(20, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define HSIO_PLL5G_STATUS1_FBCNT_DIF(x) (((x) << 4) & GENMASK(13, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define HSIO_PLL5G_STATUS1_FBCNT_DIF_M GENMASK(13, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define HSIO_PLL5G_STATUS1_FBCNT_DIF_X(x) (((x) & GENMASK(13, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define HSIO_PLL5G_STATUS1_FSM_STAT(x) (((x) << 1) & GENMASK(3, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define HSIO_PLL5G_STATUS1_FSM_STAT_M GENMASK(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define HSIO_PLL5G_STATUS1_FSM_STAT_X(x) (((x) & GENMASK(3, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define HSIO_PLL5G_STATUS1_FSM_LOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x) (((x) << 20) & GENMASK(23, 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x) (((x) & GENMASK(23, 20)) >> 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT(x) (((x) << 16) & GENMASK(19, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_M GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_X(x) (((x) & GENMASK(19, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT(x) (((x) << 4) & GENMASK(7, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_M GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_X(x) (((x) & GENMASK(7, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define HSIO_PLL5G_BIST_STAT0_PLLB_BUSY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT(x) (((x) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_M GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_X(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define HSIO_RCOMP_CFG0_PWD_ENA BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define HSIO_RCOMP_CFG0_RUN_CAL BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define HSIO_RCOMP_CFG0_SPEED_SEL(x) (((x) << 10) & GENMASK(11, 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define HSIO_RCOMP_CFG0_SPEED_SEL_M GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define HSIO_RCOMP_CFG0_SPEED_SEL_X(x) (((x) & GENMASK(11, 10)) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define HSIO_RCOMP_CFG0_MODE_SEL(x) (((x) << 8) & GENMASK(9, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define HSIO_RCOMP_CFG0_MODE_SEL_M GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define HSIO_RCOMP_CFG0_MODE_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define HSIO_RCOMP_CFG0_FORCE_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define HSIO_RCOMP_CFG0_RCOMP_VAL(x) ((x) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define HSIO_RCOMP_CFG0_RCOMP_VAL_M GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define HSIO_RCOMP_STATUS_BUSY BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define HSIO_RCOMP_STATUS_DELTA_ALERT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define HSIO_RCOMP_STATUS_RCOMP(x) ((x) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define HSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define HSIO_SYNC_ETH_CFG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC(x) (((x) << 4) & GENMASK(7, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_M GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_X(x) (((x) & GENMASK(7, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV(x) (((x) << 1) & GENMASK(3, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_M GENMASK(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_X(x) (((x) & GENMASK(3, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define HSIO_S1G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define HSIO_S1G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define HSIO_S1G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define HSIO_S1G_DES_CFG_DES_CPMD_SEL(x) (((x) << 11) & GENMASK(12, 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define HSIO_S1G_DES_CFG_DES_CPMD_SEL_M GENMASK(12, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define HSIO_S1G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(12, 11)) >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define HSIO_S1G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 8) & GENMASK(10, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(10, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define HSIO_S1G_DES_CFG_DES_BW_ANA(x) (((x) << 5) & GENMASK(7, 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define HSIO_S1G_DES_CFG_DES_BW_ANA_M GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define HSIO_S1G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(7, 5)) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define HSIO_S1G_DES_CFG_DES_SWAP_ANA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define HSIO_S1G_DES_CFG_DES_BW_HYST(x) (((x) << 1) & GENMASK(3, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define HSIO_S1G_DES_CFG_DES_BW_HYST_M GENMASK(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define HSIO_S1G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(3, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define HSIO_S1G_DES_CFG_DES_SWAP_HYST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define HSIO_S1G_IB_CFG_IB_FX100_ENA BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define HSIO_S1G_IB_CFG_ACJTAG_HYST(x) (((x) << 24) & GENMASK(26, 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define HSIO_S1G_IB_CFG_ACJTAG_HYST_M GENMASK(26, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define HSIO_S1G_IB_CFG_ACJTAG_HYST_X(x) (((x) & GENMASK(26, 24)) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define HSIO_S1G_IB_CFG_IB_DET_LEV(x) (((x) << 19) & GENMASK(21, 19))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define HSIO_S1G_IB_CFG_IB_DET_LEV_M GENMASK(21, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define HSIO_S1G_IB_CFG_IB_DET_LEV_X(x) (((x) & GENMASK(21, 19)) >> 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define HSIO_S1G_IB_CFG_IB_HYST_LEV BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define HSIO_S1G_IB_CFG_IB_ENA_DETLEV BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define HSIO_S1G_IB_CFG_IB_ENA_HYST BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define HSIO_S1G_IB_CFG_IB_EQ_GAIN(x) (((x) << 6) & GENMASK(8, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define HSIO_S1G_IB_CFG_IB_EQ_GAIN_M GENMASK(8, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define HSIO_S1G_IB_CFG_IB_EQ_GAIN_X(x) (((x) & GENMASK(8, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ(x) (((x) << 4) & GENMASK(5, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_M GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_X(x) (((x) & GENMASK(5, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define HSIO_S1G_OB_CFG_OB_SLP(x) (((x) << 17) & GENMASK(18, 17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define HSIO_S1G_OB_CFG_OB_SLP_M GENMASK(18, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define HSIO_S1G_OB_CFG_OB_SLP_X(x) (((x) & GENMASK(18, 17)) >> 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define HSIO_S1G_OB_CFG_OB_AMP_CTRL(x) (((x) << 13) & GENMASK(16, 13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define HSIO_S1G_OB_CFG_OB_AMP_CTRL_M GENMASK(16, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define HSIO_S1G_OB_CFG_OB_AMP_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL(x) (((x) << 10) & GENMASK(12, 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_M GENMASK(12, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define HSIO_S1G_OB_CFG_OB_VCM_CTRL(x) (((x) << 4) & GENMASK(7, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define HSIO_S1G_OB_CFG_OB_VCM_CTRL_M GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define HSIO_S1G_OB_CFG_OB_VCM_CTRL_X(x) (((x) & GENMASK(7, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define HSIO_S1G_SER_CFG_SER_IDLE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define HSIO_S1G_SER_CFG_SER_DEEMPH BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define HSIO_S1G_SER_CFG_SER_CPMD_SEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define HSIO_S1G_SER_CFG_SER_SWAP_CPMD BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define HSIO_S1G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define HSIO_S1G_SER_CFG_SER_ALISEL_M GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define HSIO_S1G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define HSIO_S1G_SER_CFG_SER_ENHYS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define HSIO_S1G_SER_CFG_SER_BIG_WIN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define HSIO_S1G_SER_CFG_SER_EN_WIN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define HSIO_S1G_SER_CFG_SER_ENALI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define HSIO_S1G_COMMON_CFG_SYS_RST BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define HSIO_S1G_COMMON_CFG_ENA_LANE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define HSIO_S1G_COMMON_CFG_PWD_RX BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define HSIO_S1G_COMMON_CFG_PWD_TX BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define HSIO_S1G_COMMON_CFG_LANE_CTRL(x) (((x) << 13) & GENMASK(15, 13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define HSIO_S1G_COMMON_CFG_LANE_CTRL_M GENMASK(15, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define HSIO_S1G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(15, 13)) >> 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define HSIO_S1G_COMMON_CFG_ENA_DIRECT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define HSIO_S1G_COMMON_CFG_ENA_ELOOP BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define HSIO_S1G_COMMON_CFG_ENA_FLOOP BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define HSIO_S1G_COMMON_CFG_ENA_ILOOP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define HSIO_S1G_COMMON_CFG_ENA_PLOOP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define HSIO_S1G_COMMON_CFG_HRATE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define HSIO_S1G_COMMON_CFG_IF_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2 BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2 BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 8) & GENMASK(15, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(15, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define HSIO_S1G_PLL_CFG_PLL_FSM_ENA BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define HSIO_S1G_PLL_STATUS_PLL_CAL_ERR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define HSIO_S1G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define HSIO_S1G_DFT_CFG0_LAZYBIT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define HSIO_S1G_DFT_CFG0_INV_DIS BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define HSIO_S1G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define HSIO_S1G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define HSIO_S1G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define HSIO_S1G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define HSIO_S1G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define HSIO_S1G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define HSIO_S1G_DFT_CFG0_RX_DFT_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define HSIO_S1G_DFT_CFG0_TX_DFT_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define HSIO_S1G_DFT_CFG1_TX_JI_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define HSIO_S1G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define HSIO_S1G_DFT_CFG1_TX_FREQOFF_DIR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define HSIO_S1G_DFT_CFG2_RX_JI_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define HSIO_S1G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define HSIO_S1G_DFT_CFG2_RX_FREQOFF_DIR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(17, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(17, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define HSIO_S1G_MISC_CFG_RX_LPI_MODE_ENA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define HSIO_S1G_MISC_CFG_TX_LPI_MODE_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define HSIO_S1G_MISC_CFG_RX_DATA_INV_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define HSIO_S1G_MISC_CFG_TX_DATA_INV_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define HSIO_S1G_MISC_CFG_LANE_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define HSIO_S1G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define HSIO_S1G_DFT_STATUS_PLL_BIST_FAILED BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define HSIO_S1G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define HSIO_S1G_DFT_STATUS_BIST_ACTIVE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define HSIO_S1G_DFT_STATUS_BIST_NOSYNC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define HSIO_S1G_DFT_STATUS_BIST_COMPLETE_N BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define HSIO_S1G_DFT_STATUS_BIST_ERROR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(x) ((x) & GENMASK(8, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M GENMASK(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define HSIO_S6G_DIG_CFG_GP(x) (((x) << 16) & GENMASK(18, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define HSIO_S6G_DIG_CFG_GP_M GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define HSIO_S6G_DIG_CFG_GP_X(x) (((x) & GENMASK(18, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define HSIO_S6G_DIG_CFG_TX_BIT_DOUBLING_MODE_ENA BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define HSIO_S6G_DIG_CFG_SIGDET_TESTMODE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define HSIO_S6G_DIG_CFG_SIGDET_AST(x) (((x) << 3) & GENMASK(5, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define HSIO_S6G_DIG_CFG_SIGDET_AST_M GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define HSIO_S6G_DIG_CFG_SIGDET_AST_X(x) (((x) & GENMASK(5, 3)) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define HSIO_S6G_DIG_CFG_SIGDET_DST(x) ((x) & GENMASK(2, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define HSIO_S6G_DIG_CFG_SIGDET_DST_M GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define HSIO_S6G_DFT_CFG0_LAZYBIT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define HSIO_S6G_DFT_CFG0_INV_DIS BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define HSIO_S6G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define HSIO_S6G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define HSIO_S6G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define HSIO_S6G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define HSIO_S6G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define HSIO_S6G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define HSIO_S6G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define HSIO_S6G_DFT_CFG0_RX_PDSENS_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define HSIO_S6G_DFT_CFG0_RX_DFT_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define HSIO_S6G_DFT_CFG0_TX_DFT_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define HSIO_S6G_DFT_CFG1_TX_JI_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define HSIO_S6G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define HSIO_S6G_DFT_CFG1_TX_FREQOFF_DIR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define HSIO_S6G_DFT_CFG2_RX_JI_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define HSIO_S6G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define HSIO_S6G_DFT_CFG2_RX_FREQOFF_DIR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(19, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(19, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define HSIO_S6G_MISC_CFG_SEL_RECO_CLK(x) (((x) << 13) & GENMASK(14, 13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_M GENMASK(14, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_X(x) (((x) & GENMASK(14, 13)) >> 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define HSIO_S6G_MISC_CFG_RX_BUS_FLIP_ENA BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define HSIO_S6G_MISC_CFG_TX_BUS_FLIP_ENA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define HSIO_S6G_MISC_CFG_RX_DATA_INV_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define HSIO_S6G_MISC_CFG_TX_DATA_INV_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define HSIO_S6G_MISC_CFG_LANE_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M GENMASK(28, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1(x) (((x) << 18) & GENMASK(22, 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_M GENMASK(22, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_X(x) (((x) & GENMASK(22, 18)) >> 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC(x) (((x) << 13) & GENMASK(17, 13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_M GENMASK(17, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_X(x) (((x) & GENMASK(17, 13)) >> 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_M GENMASK(8, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define HSIO_S6G_DFT_STATUS_PRBS_SYNC_STAT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define HSIO_S6G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define HSIO_S6G_DFT_STATUS_PLL_BIST_FAILED BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define HSIO_S6G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define HSIO_S6G_DFT_STATUS_BIST_ACTIVE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define HSIO_S6G_DFT_STATUS_BIST_NOSYNC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define HSIO_S6G_DFT_STATUS_BIST_COMPLETE_N BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define HSIO_S6G_DFT_STATUS_BIST_ERROR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define HSIO_S6G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define HSIO_S6G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define HSIO_S6G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define HSIO_S6G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 10) & GENMASK(12, 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_M GENMASK(12, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define HSIO_S6G_DES_CFG_DES_CPMD_SEL(x) (((x) << 8) & GENMASK(9, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define HSIO_S6G_DES_CFG_DES_CPMD_SEL_M GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define HSIO_S6G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define HSIO_S6G_DES_CFG_DES_BW_HYST(x) (((x) << 5) & GENMASK(7, 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define HSIO_S6G_DES_CFG_DES_BW_HYST_M GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define HSIO_S6G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(7, 5)) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define HSIO_S6G_DES_CFG_DES_SWAP_HYST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define HSIO_S6G_DES_CFG_DES_BW_ANA(x) (((x) << 1) & GENMASK(3, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define HSIO_S6G_DES_CFG_DES_BW_ANA_M GENMASK(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define HSIO_S6G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(3, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define HSIO_S6G_DES_CFG_DES_SWAP_ANA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define HSIO_S6G_IB_CFG_IB_SOFSI(x) (((x) << 29) & GENMASK(30, 29))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define HSIO_S6G_IB_CFG_IB_SOFSI_M GENMASK(30, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define HSIO_S6G_IB_CFG_IB_SOFSI_X(x) (((x) & GENMASK(30, 29)) >> 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define HSIO_S6G_IB_CFG_IB_VBULK_SEL BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define HSIO_S6G_IB_CFG_IB_RTRM_ADJ(x) (((x) << 24) & GENMASK(27, 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_M GENMASK(27, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_X(x) (((x) & GENMASK(27, 24)) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define HSIO_S6G_IB_CFG_IB_ICML_ADJ(x) (((x) << 20) & GENMASK(23, 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define HSIO_S6G_IB_CFG_IB_ICML_ADJ_M GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define HSIO_S6G_IB_CFG_IB_ICML_ADJ_X(x) (((x) & GENMASK(23, 20)) >> 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL(x) (((x) << 18) & GENMASK(19, 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_M GENMASK(19, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_X(x) (((x) & GENMASK(19, 18)) >> 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(x) (((x) << 15) & GENMASK(17, 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M GENMASK(17, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_X(x) (((x) & GENMASK(17, 15)) >> 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP(x) (((x) << 13) & GENMASK(14, 13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_M GENMASK(14, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_X(x) (((x) & GENMASK(14, 13)) >> 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID(x) (((x) << 11) & GENMASK(12, 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_M GENMASK(12, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_X(x) (((x) & GENMASK(12, 11)) >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP(x) (((x) << 9) & GENMASK(10, 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_M GENMASK(10, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_X(x) (((x) & GENMASK(10, 9)) >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(x) (((x) << 7) & GENMASK(8, 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M GENMASK(8, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_X(x) (((x) & GENMASK(8, 7)) >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define HSIO_S6G_IB_CFG_IB_ANA_TEST_ENA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define HSIO_S6G_IB_CFG_IB_SIG_DET_ENA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define HSIO_S6G_IB_CFG_IB_CONCUR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define HSIO_S6G_IB_CFG_IB_CAL_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define HSIO_S6G_IB_CFG_IB_SAM_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define HSIO_S6G_IB_CFG_IB_EQZ_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define HSIO_S6G_IB_CFG_IB_REG_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define HSIO_S6G_IB_CFG1_IB_TJTAG(x) (((x) << 17) & GENMASK(21, 17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define HSIO_S6G_IB_CFG1_IB_TJTAG_M GENMASK(21, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define HSIO_S6G_IB_CFG1_IB_TJTAG_X(x) (((x) & GENMASK(21, 17)) >> 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define HSIO_S6G_IB_CFG1_IB_TSDET(x) (((x) << 12) & GENMASK(16, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define HSIO_S6G_IB_CFG1_IB_TSDET_M GENMASK(16, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define HSIO_S6G_IB_CFG1_IB_TSDET_X(x) (((x) & GENMASK(16, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define HSIO_S6G_IB_CFG1_IB_SCALY(x) (((x) << 8) & GENMASK(11, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define HSIO_S6G_IB_CFG1_IB_SCALY_M GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define HSIO_S6G_IB_CFG1_IB_SCALY_X(x) (((x) & GENMASK(11, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define HSIO_S6G_IB_CFG1_IB_FILT_HP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define HSIO_S6G_IB_CFG1_IB_FILT_MID BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define HSIO_S6G_IB_CFG1_IB_FILT_LP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define HSIO_S6G_IB_CFG1_IB_FILT_OFFSET BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define HSIO_S6G_IB_CFG1_IB_FRC_HP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define HSIO_S6G_IB_CFG1_IB_FRC_MID BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define HSIO_S6G_IB_CFG1_IB_FRC_LP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define HSIO_S6G_IB_CFG1_IB_FRC_OFFSET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define HSIO_S6G_IB_CFG2_IB_TINFV(x) (((x) << 27) & GENMASK(29, 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define HSIO_S6G_IB_CFG2_IB_TINFV_M GENMASK(29, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define HSIO_S6G_IB_CFG2_IB_TINFV_X(x) (((x) & GENMASK(29, 27)) >> 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define HSIO_S6G_IB_CFG2_IB_OINFI(x) (((x) << 22) & GENMASK(26, 22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define HSIO_S6G_IB_CFG2_IB_OINFI_M GENMASK(26, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define HSIO_S6G_IB_CFG2_IB_OINFI_X(x) (((x) & GENMASK(26, 22)) >> 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define HSIO_S6G_IB_CFG2_IB_TAUX(x) (((x) << 19) & GENMASK(21, 19))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define HSIO_S6G_IB_CFG2_IB_TAUX_M GENMASK(21, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define HSIO_S6G_IB_CFG2_IB_TAUX_X(x) (((x) & GENMASK(21, 19)) >> 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define HSIO_S6G_IB_CFG2_IB_OINFS(x) (((x) << 16) & GENMASK(18, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define HSIO_S6G_IB_CFG2_IB_OINFS_M GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define HSIO_S6G_IB_CFG2_IB_OINFS_X(x) (((x) & GENMASK(18, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define HSIO_S6G_IB_CFG2_IB_OCALS(x) (((x) << 10) & GENMASK(15, 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define HSIO_S6G_IB_CFG2_IB_OCALS_M GENMASK(15, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define HSIO_S6G_IB_CFG2_IB_OCALS_X(x) (((x) & GENMASK(15, 10)) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define HSIO_S6G_IB_CFG2_IB_TCALV(x) (((x) << 5) & GENMASK(9, 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define HSIO_S6G_IB_CFG2_IB_TCALV_M GENMASK(9, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define HSIO_S6G_IB_CFG2_IB_TCALV_X(x) (((x) & GENMASK(9, 5)) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define HSIO_S6G_IB_CFG2_IB_UMAX(x) (((x) << 3) & GENMASK(4, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define HSIO_S6G_IB_CFG2_IB_UMAX_M GENMASK(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define HSIO_S6G_IB_CFG2_IB_UMAX_X(x) (((x) & GENMASK(4, 3)) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define HSIO_S6G_IB_CFG2_IB_UREG(x) ((x) & GENMASK(2, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define HSIO_S6G_IB_CFG2_IB_UREG_M GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define HSIO_S6G_IB_CFG3_IB_INI_HP(x) (((x) << 18) & GENMASK(23, 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define HSIO_S6G_IB_CFG3_IB_INI_HP_M GENMASK(23, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define HSIO_S6G_IB_CFG3_IB_INI_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define HSIO_S6G_IB_CFG3_IB_INI_MID(x) (((x) << 12) & GENMASK(17, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define HSIO_S6G_IB_CFG3_IB_INI_MID_M GENMASK(17, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define HSIO_S6G_IB_CFG3_IB_INI_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define HSIO_S6G_IB_CFG3_IB_INI_LP(x) (((x) << 6) & GENMASK(11, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define HSIO_S6G_IB_CFG3_IB_INI_LP_M GENMASK(11, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define HSIO_S6G_IB_CFG3_IB_INI_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define HSIO_S6G_IB_CFG3_IB_INI_OFFSET(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define HSIO_S6G_IB_CFG4_IB_MAX_HP(x) (((x) << 18) & GENMASK(23, 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define HSIO_S6G_IB_CFG4_IB_MAX_HP_M GENMASK(23, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define HSIO_S6G_IB_CFG4_IB_MAX_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define HSIO_S6G_IB_CFG4_IB_MAX_MID(x) (((x) << 12) & GENMASK(17, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define HSIO_S6G_IB_CFG4_IB_MAX_MID_M GENMASK(17, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define HSIO_S6G_IB_CFG4_IB_MAX_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define HSIO_S6G_IB_CFG4_IB_MAX_LP(x) (((x) << 6) & GENMASK(11, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define HSIO_S6G_IB_CFG4_IB_MAX_LP_M GENMASK(11, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define HSIO_S6G_IB_CFG4_IB_MAX_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define HSIO_S6G_IB_CFG5_IB_MIN_HP(x) (((x) << 18) & GENMASK(23, 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define HSIO_S6G_IB_CFG5_IB_MIN_HP_M GENMASK(23, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define HSIO_S6G_IB_CFG5_IB_MIN_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define HSIO_S6G_IB_CFG5_IB_MIN_MID(x) (((x) << 12) & GENMASK(17, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define HSIO_S6G_IB_CFG5_IB_MIN_MID_M GENMASK(17, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define HSIO_S6G_IB_CFG5_IB_MIN_MID_X(x) (((x) & GENMASK(17, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define HSIO_S6G_IB_CFG5_IB_MIN_LP(x) (((x) << 6) & GENMASK(11, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define HSIO_S6G_IB_CFG5_IB_MIN_LP_M GENMASK(11, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define HSIO_S6G_IB_CFG5_IB_MIN_LP_X(x) (((x) & GENMASK(11, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define HSIO_S6G_OB_CFG_OB_IDLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define HSIO_S6G_OB_CFG_OB_ENA1V_MODE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define HSIO_S6G_OB_CFG_OB_POL BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define HSIO_S6G_OB_CFG_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define HSIO_S6G_OB_CFG_OB_POST0_M GENMASK(28, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define HSIO_S6G_OB_CFG_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define HSIO_S6G_OB_CFG_OB_PREC(x) (((x) << 18) & GENMASK(22, 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define HSIO_S6G_OB_CFG_OB_PREC_M GENMASK(22, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define HSIO_S6G_OB_CFG_OB_PREC_X(x) (((x) & GENMASK(22, 18)) >> 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define HSIO_S6G_OB_CFG_OB_R_ADJ_MUX BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define HSIO_S6G_OB_CFG_OB_R_ADJ_PDR BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define HSIO_S6G_OB_CFG_OB_POST1(x) (((x) << 11) & GENMASK(15, 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define HSIO_S6G_OB_CFG_OB_POST1_M GENMASK(15, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define HSIO_S6G_OB_CFG_OB_POST1_X(x) (((x) & GENMASK(15, 11)) >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define HSIO_S6G_OB_CFG_OB_R_COR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define HSIO_S6G_OB_CFG_OB_SEL_RCTRL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define HSIO_S6G_OB_CFG_OB_SR_H BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define HSIO_S6G_OB_CFG_OB_SR(x) (((x) << 4) & GENMASK(7, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define HSIO_S6G_OB_CFG_OB_SR_M GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define HSIO_S6G_OB_CFG_OB_SR_X(x) (((x) & GENMASK(7, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define HSIO_S6G_OB_CFG1_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define HSIO_S6G_OB_CFG1_OB_ENA_CAS_M GENMASK(8, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define HSIO_S6G_OB_CFG1_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define HSIO_S6G_OB_CFG1_OB_LEV(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define HSIO_S6G_OB_CFG1_OB_LEV_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define HSIO_S6G_SER_CFG_SER_4TAP_ENA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define HSIO_S6G_SER_CFG_SER_CPMD_SEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define HSIO_S6G_SER_CFG_SER_SWAP_CPMD BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define HSIO_S6G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define HSIO_S6G_SER_CFG_SER_ALISEL_M GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define HSIO_S6G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define HSIO_S6G_SER_CFG_SER_ENHYS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define HSIO_S6G_SER_CFG_SER_BIG_WIN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define HSIO_S6G_SER_CFG_SER_EN_WIN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define HSIO_S6G_SER_CFG_SER_ENALI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define HSIO_S6G_COMMON_CFG_SYS_RST BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define HSIO_S6G_COMMON_CFG_SE_DIV2_ENA BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define HSIO_S6G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define HSIO_S6G_COMMON_CFG_ENA_LANE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define HSIO_S6G_COMMON_CFG_PWD_RX BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define HSIO_S6G_COMMON_CFG_PWD_TX BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define HSIO_S6G_COMMON_CFG_LANE_CTRL(x) (((x) << 9) & GENMASK(11, 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define HSIO_S6G_COMMON_CFG_LANE_CTRL_M GENMASK(11, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define HSIO_S6G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(11, 9)) >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define HSIO_S6G_COMMON_CFG_ENA_DIRECT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define HSIO_S6G_COMMON_CFG_ENA_ELOOP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define HSIO_S6G_COMMON_CFG_ENA_FLOOP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define HSIO_S6G_COMMON_CFG_ENA_ILOOP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define HSIO_S6G_COMMON_CFG_ENA_PLOOP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define HSIO_S6G_COMMON_CFG_HRATE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define HSIO_S6G_COMMON_CFG_QRATE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define HSIO_S6G_COMMON_CFG_IF_MODE(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define HSIO_S6G_COMMON_CFG_IF_MODE_M GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS(x) (((x) << 16) & GENMASK(17, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_M GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_X(x) (((x) & GENMASK(17, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define HSIO_S6G_PLL_CFG_PLL_DIV4 BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define HSIO_S6G_PLL_CFG_PLL_ENA_ROT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(13, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define HSIO_S6G_PLL_CFG_PLL_FSM_ENA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define HSIO_S6G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define HSIO_S6G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define HSIO_S6G_PLL_CFG_PLL_RB_DATA_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define HSIO_S6G_PLL_CFG_PLL_ROT_DIR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define HSIO_S6G_PLL_CFG_PLL_ROT_FRQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_N BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_P BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_CLK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define HSIO_S6G_ACJTAG_CFG_OB_DIRECT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define HSIO_S6G_ACJTAG_CFG_ACJTAG_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define HSIO_S6G_GP_CFG_GP_MSB(x) (((x) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define HSIO_S6G_GP_CFG_GP_MSB_M GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define HSIO_S6G_GP_CFG_GP_MSB_X(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define HSIO_S6G_GP_CFG_GP_LSB(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define HSIO_S6G_GP_CFG_GP_LSB_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define HSIO_S6G_IB_STATUS0_IB_CAL_DONE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define HSIO_S6G_IB_STATUS0_IB_HP_GAIN_ACT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define HSIO_S6G_IB_STATUS0_IB_MID_GAIN_ACT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define HSIO_S6G_IB_STATUS0_IB_LP_GAIN_ACT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define HSIO_S6G_IB_STATUS0_IB_OFFSET_ACT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define HSIO_S6G_IB_STATUS0_IB_OFFSET_VLD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define HSIO_S6G_IB_STATUS0_IB_OFFSET_ERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define HSIO_S6G_IB_STATUS0_IB_OFFSDIR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define HSIO_S6G_IB_STATUS0_IB_SIG_DET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT(x) (((x) << 18) & GENMASK(23, 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M GENMASK(23, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X(x) (((x) & GENMASK(23, 18)) >> 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT(x) (((x) << 12) & GENMASK(17, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_M GENMASK(17, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_X(x) (((x) & GENMASK(17, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT(x) (((x) << 6) & GENMASK(11, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_M GENMASK(11, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_X(x) (((x) & GENMASK(11, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_N BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_P BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define HSIO_S6G_ACJTAG_STATUS_IB_DIRECT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define HSIO_S6G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define HSIO_S6G_PLL_STATUS_PLL_CAL_ERR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define HSIO_S6G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define HSIO_S6G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define HSIO_S6G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define HSIO_S6G_REVID_SERDES_REV(x) (((x) << 26) & GENMASK(31, 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define HSIO_S6G_REVID_SERDES_REV_M GENMASK(31, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define HSIO_S6G_REVID_SERDES_REV_X(x) (((x) & GENMASK(31, 26)) >> 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define HSIO_S6G_REVID_RCPLL_REV(x) (((x) << 21) & GENMASK(25, 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define HSIO_S6G_REVID_RCPLL_REV_M GENMASK(25, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define HSIO_S6G_REVID_RCPLL_REV_X(x) (((x) & GENMASK(25, 21)) >> 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define HSIO_S6G_REVID_SER_REV(x) (((x) << 16) & GENMASK(20, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define HSIO_S6G_REVID_SER_REV_M GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define HSIO_S6G_REVID_SER_REV_X(x) (((x) & GENMASK(20, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define HSIO_S6G_REVID_DES_REV(x) (((x) << 10) & GENMASK(15, 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define HSIO_S6G_REVID_DES_REV_M GENMASK(15, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define HSIO_S6G_REVID_DES_REV_X(x) (((x) & GENMASK(15, 10)) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define HSIO_S6G_REVID_OB_REV(x) (((x) << 5) & GENMASK(9, 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define HSIO_S6G_REVID_OB_REV_M GENMASK(9, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define HSIO_S6G_REVID_OB_REV_X(x) (((x) & GENMASK(9, 5)) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define HSIO_S6G_REVID_IB_REV(x) ((x) & GENMASK(4, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define HSIO_S6G_REVID_IB_REV_M GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(x) ((x) & GENMASK(24, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR_M GENMASK(24, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define HSIO_HW_CFG_DEV2G5_10_MODE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define HSIO_HW_CFG_DEV1G_9_MODE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define HSIO_HW_CFG_DEV1G_6_MODE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define HSIO_HW_CFG_DEV1G_5_MODE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define HSIO_HW_CFG_DEV1G_4_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define HSIO_HW_CFG_PCIE_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define HSIO_HW_CFG_QSGMII_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define HSIO_HW_QSGMII_CFG_SHYST_DIS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define HSIO_HW_QSGMII_CFG_E_DET_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define HSIO_HW_QSGMII_CFG_USE_I1_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define HSIO_HW_QSGMII_CFG_FLIP_LANES BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS(x) (((x) << 1) & GENMASK(6, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_M GENMASK(6, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_X(x) (((x) & GENMASK(6, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define HSIO_HW_QSGMII_STAT_SYNC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define HSIO_CLK_CFG_CLKDIV_PHY(x) (((x) << 1) & GENMASK(8, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define HSIO_CLK_CFG_CLKDIV_PHY_M GENMASK(8, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define HSIO_CLK_CFG_CLKDIV_PHY_X(x) (((x) & GENMASK(8, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define HSIO_CLK_CFG_CLKDIV_PHY_DIS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define HSIO_TEMP_SENSOR_CTRL_FORCE_TEMP_RD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define HSIO_TEMP_SENSOR_CTRL_FORCE_RUN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define HSIO_TEMP_SENSOR_CTRL_FORCE_NO_RST BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define HSIO_TEMP_SENSOR_CTRL_FORCE_POWER_UP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define HSIO_TEMP_SENSOR_CTRL_FORCE_CLK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define HSIO_TEMP_SENSOR_CFG_RUN_WID(x) (((x) << 8) & GENMASK(15, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define HSIO_TEMP_SENSOR_CFG_RUN_WID_M GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define HSIO_TEMP_SENSOR_CFG_RUN_WID_X(x) (((x) & GENMASK(15, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define HSIO_TEMP_SENSOR_STAT_TEMP_VALID BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define HSIO_TEMP_SENSOR_STAT_TEMP(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define HSIO_TEMP_SENSOR_STAT_TEMP_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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