^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Microsemi Ocelot Switch driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017 Microsemi Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _MSCC_OCELOT_DEV_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _MSCC_OCELOT_DEV_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DEV_CLOCK_CFG_PORT_RST BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DEV_CLOCK_CFG_PHY_RST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DEV_PORT_MISC_HDX_FAST_DIS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DEV_EEE_CFG_EEE_ENA BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DEV_EEE_CFG_PORT_LPI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) (((x) << 4) & GENMASK(11, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M GENMASK(11, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x) (((x) & GENMASK(11, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x) ((x) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DEV_MAC_MODE_CFG_FDX_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DEV_MAC_TAGS_CFG_TAG_ID(x) (((x) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DEV_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DEV_MAC_TAGS_CFG_TAG_ID_X(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DEV_MAC_IFG_CFG_REDUCED_TX_IFG BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DEV_MAC_IFG_CFG_TX_IFG(x) (((x) << 8) & GENMASK(12, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DEV_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DEV_MAC_IFG_CFG_TX_IFG_X(x) (((x) & GENMASK(12, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DEV_MAC_IFG_CFG_RX_IFG2(x) (((x) << 4) & GENMASK(7, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DEV_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DEV_MAC_IFG_CFG_RX_IFG2_X(x) (((x) & GENMASK(7, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DEV_MAC_IFG_CFG_RX_IFG1(x) ((x) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DEV_MAC_IFG_CFG_RX_IFG1_M GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DEV_MAC_HDX_CFG_OB_ENA BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DEV_MAC_HDX_CFG_WEXC_DIS BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DEV_MAC_HDX_CFG_SEED(x) (((x) << 16) & GENMASK(23, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DEV_MAC_HDX_CFG_SEED_M GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DEV_MAC_HDX_CFG_SEED_X(x) (((x) & GENMASK(23, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DEV_MAC_HDX_CFG_LATE_COL_POS(x) ((x) & GENMASK(6, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DEV_MAC_HDX_CFG_LATE_COL_POS_M GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DEV_MAC_DBG_CFG_TBI_MODE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DEV_MAC_STICKY_RX_JUNK_STICKY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DEV_MAC_STICKY_TX_JAM_STICKY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DEV_MAC_STICKY_TX_ABORT_STICKY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PCS1G_CFG_LINK_STATUS_TYPE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCS1G_CFG_PCS_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCS1G_SD_CFG_SD_SEL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCS1G_SD_CFG_SD_POL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PCS1G_SD_CFG_SD_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCS1G_ANEG_CFG_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCS1G_ANEG_CFG_ADV_ABILITY_M GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PCS1G_ANEG_CFG_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCS1G_ANEG_CFG_ANEG_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCS1G_ANEG_NP_CFG_NP_TX(x) (((x) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCS1G_ANEG_NP_CFG_NP_TX_M GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCS1G_ANEG_NP_CFG_NP_TX_X(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PCS1G_LB_CFG_RA_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCS1G_DBG_CFG_UDLT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PCS1G_CDET_CFG_CDET_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PCS1G_ANEG_STATUS_PR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PCS1G_LINK_STATUS_DELAY_VAR(x) (((x) << 12) & GENMASK(15, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PCS1G_LINK_STATUS_DELAY_VAR_M GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PCS1G_LINK_STATUS_DELAY_VAR_X(x) (((x) & GENMASK(15, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PCS1G_LINK_STATUS_LINK_STATUS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PCS1G_LINK_STATUS_SYNC_STATUS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PCS1G_STICKY_LINK_DOWN_STICKY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PCS1G_LPI_CFG_QSGMII_MS_SEL BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PCS1G_LPI_CFG_RX_LPI_OUT_DIS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PCS1G_LPI_CFG_LPI_TESTMODE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PCS1G_LPI_CFG_LPI_RX_WTIM(x) (((x) << 4) & GENMASK(5, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PCS1G_LPI_CFG_LPI_RX_WTIM_M GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x) (((x) & GENMASK(5, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PCS1G_LPI_CFG_TX_ASSERT_LPIDLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PCS1G_LPI_STATUS_RX_LPI_FAIL BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PCS1G_LPI_STATUS_RX_QUIET BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PCS1G_LPI_STATUS_RX_LPI_MODE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PCS1G_LPI_STATUS_TX_QUIET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PCS1G_LPI_STATUS_TX_LPI_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x) (((x) << 8) & GENMASK(15, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x) (((x) & GENMASK(15, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PCS1G_TSTPAT_STATUS_JTP_ERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PCS1G_TSTPAT_STATUS_JTP_LOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DEV_PCS_FX100_CFG_SD_SEL BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DEV_PCS_FX100_CFG_SD_POL BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DEV_PCS_FX100_CFG_SD_ENA BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DEV_PCS_FX100_CFG_LOOPBACK_ENA BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DEV_PCS_FX100_CFG_SWAP_MII_ENA BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DEV_PCS_FX100_CFG_RXBITSEL(x) (((x) << 12) & GENMASK(15, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DEV_PCS_FX100_CFG_RXBITSEL_M GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DEV_PCS_FX100_CFG_RXBITSEL_X(x) (((x) & GENMASK(15, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DEV_PCS_FX100_CFG_SIGDET_CFG(x) (((x) << 9) & GENMASK(10, 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DEV_PCS_FX100_CFG_SIGDET_CFG_M GENMASK(10, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x) (((x) & GENMASK(10, 9)) >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DEV_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x) (((x) << 4) & GENMASK(7, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x) (((x) & GENMASK(7, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DEV_PCS_FX100_CFG_FEFCHK_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DEV_PCS_FX100_CFG_FEFGEN_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DEV_PCS_FX100_CFG_PCS_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x) (((x) << 8) & GENMASK(11, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x) (((x) & GENMASK(11, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DEV_PCS_FX100_STATUS_FEF_STATUS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DEV_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DEV_PCS_FX100_STATUS_SYNC_STATUS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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