^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Microsemi Ocelot Switch driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017 Microsemi Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _MSCC_OCELOT_ANA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _MSCC_OCELOT_ANA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ANA_ANAGEFIL_PID_EN BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ANA_ANAGEFIL_VID_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ANA_STORMLIMIT_CFG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ANA_AUTOAGE_AGE_FAST BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ANA_AUTOAGE_AGE_PERIOD(x) (((x) << 1) & GENMASK(20, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ANA_AUTOAGE_AGE_PERIOD_M GENMASK(20, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ANA_AUTOAGE_AGE_PERIOD_X(x) (((x) & GENMASK(20, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ANA_MACTOPTIONS_SHADOW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ANA_AGENCTRL_FID_MASK(x) (((x) << 12) & GENMASK(23, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ANA_AGENCTRL_FID_MASK_M GENMASK(23, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ANA_AGENCTRL_FID_MASK_X(x) (((x) & GENMASK(23, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ANA_AGENCTRL_IGNORE_DMAC_FLAGS BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ANA_AGENCTRL_IGNORE_SMAC_FLAGS BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ANA_AGENCTRL_FLOOD_SPECIAL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ANA_AGENCTRL_FLOOD_IGNORE_VLAN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ANA_AGENCTRL_MIRROR_CPU BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ANA_AGENCTRL_LEARN_CPU_COPY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ANA_AGENCTRL_LEARN_FWD_KILL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ANA_AGENCTRL_LEARN_IGNORE_VLAN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ANA_AGENCTRL_CPU_CPU_KILL_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ANA_AGENCTRL_GREEN_COUNT_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ANA_AGENCTRL_YELLOW_COUNT_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ANA_AGENCTRL_RED_COUNT_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ANA_FLOODING_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ANA_FLOODING_FLD_UNICAST(x) (((x) << 12) & GENMASK(17, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ANA_FLOODING_FLD_UNICAST_M GENMASK(17, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ANA_FLOODING_FLD_UNICAST_X(x) (((x) & GENMASK(17, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ANA_FLOODING_FLD_BROADCAST(x) (((x) << 6) & GENMASK(11, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ANA_FLOODING_FLD_BROADCAST_X(x) (((x) & GENMASK(11, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ANA_FLOODING_FLD_MULTICAST_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ANA_FLOODING_IPMC_FLD_MC4_CTRL(x) (((x) << 18) & GENMASK(23, 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_M GENMASK(23, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_X(x) (((x) & GENMASK(23, 18)) >> 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ANA_FLOODING_IPMC_FLD_MC4_DATA(x) (((x) << 12) & GENMASK(17, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ANA_FLOODING_IPMC_FLD_MC4_DATA_M GENMASK(17, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ANA_FLOODING_IPMC_FLD_MC4_DATA_X(x) (((x) & GENMASK(17, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ANA_FLOODING_IPMC_FLD_MC6_CTRL(x) (((x) << 6) & GENMASK(11, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_X(x) (((x) & GENMASK(11, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ANA_FLOODING_IPMC_FLD_MC6_DATA_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ANA_SFLOW_CFG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ANA_SFLOW_CFG_SF_RATE(x) (((x) << 2) & GENMASK(13, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ANA_SFLOW_CFG_SF_RATE_M GENMASK(13, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ANA_SFLOW_CFG_SF_RATE_X(x) (((x) & GENMASK(13, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ANA_SFLOW_CFG_SF_SAMPLE_RX BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ANA_SFLOW_CFG_SF_SAMPLE_TX BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ANA_PORT_MODE_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ANA_PORT_MODE_REDTAG_PARSE_CFG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ANA_PORT_MODE_VLAN_PARSE_CFG(x) (((x) << 1) & GENMASK(2, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ANA_PORT_MODE_VLAN_PARSE_CFG_M GENMASK(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ANA_PORT_MODE_VLAN_PARSE_CFG_X(x) (((x) & GENMASK(2, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ANA_PORT_MODE_L3_PARSE_CFG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ANA_CUT_THRU_CFG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ANA_PGID_PGID_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ANA_PGID_PGID_PGID_M GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ANA_PGID_PGID_CPUQ_DST_PGID(x) (((x) << 27) & GENMASK(29, 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ANA_PGID_PGID_CPUQ_DST_PGID_M GENMASK(29, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ANA_PGID_PGID_CPUQ_DST_PGID_X(x) (((x) & GENMASK(29, 27)) >> 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ANA_TABLES_MACHDATA_VID(x) (((x) << 16) & GENMASK(28, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ANA_TABLES_MACHDATA_VID_M GENMASK(28, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ANA_TABLES_MACHDATA_VID_X(x) (((x) & GENMASK(28, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ANA_TABLES_MACHDATA_MACHDATA(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ANA_TABLES_MACHDATA_MACHDATA_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ANA_TABLES_STREAMDATA_SSID_VALID BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ANA_TABLES_STREAMDATA_SSID(x) (((x) << 9) & GENMASK(15, 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ANA_TABLES_STREAMDATA_SSID_M GENMASK(15, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ANA_TABLES_STREAMDATA_SSID_X(x) (((x) & GENMASK(15, 9)) >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ANA_TABLES_STREAMDATA_SFID_VALID BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ANA_TABLES_STREAMDATA_SFID_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ANA_TABLES_MACACCESS_MAC_CPU_COPY BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ANA_TABLES_MACACCESS_SRC_KILL BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ANA_TABLES_MACACCESS_IGNORE_VLAN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ANA_TABLES_MACACCESS_AGED_FLAG BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ANA_TABLES_MACACCESS_VALID BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ANA_TABLES_MACACCESS_ENTRYTYPE(x) (((x) << 9) & GENMASK(10, 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ANA_TABLES_MACACCESS_ENTRYTYPE_M GENMASK(10, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ANA_TABLES_MACACCESS_ENTRYTYPE_X(x) (((x) & GENMASK(10, 9)) >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ANA_TABLES_MACACCESS_DEST_IDX(x) (((x) << 3) & GENMASK(8, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ANA_TABLES_MACACCESS_DEST_IDX_M GENMASK(8, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ANA_TABLES_MACACCESS_DEST_IDX_X(x) (((x) & GENMASK(8, 3)) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) ((x) & GENMASK(2, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MACACCESS_CMD_IDLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MACACCESS_CMD_LEARN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MACACCESS_CMD_FORGET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MACACCESS_CMD_AGE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MACACCESS_CMD_GET_NEXT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MACACCESS_CMD_INIT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MACACCESS_CMD_READ 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MACACCESS_CMD_WRITE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(x) (((x) << 2) & GENMASK(13, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_M GENMASK(13, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_X(x) (((x) & GENMASK(13, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ANA_TABLES_VLANACCESS_CMD_IDLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ANA_TABLES_VLANACCESS_CMD_WRITE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ANA_TABLES_VLANACCESS_CMD_INIT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ANA_TABLES_VLANTIDX_VLAN_SEC_FWD_ENA BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ANA_TABLES_VLANTIDX_VLAN_FLOOD_DIS BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ANA_TABLES_VLANTIDX_VLAN_PRIV_VLAN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ANA_TABLES_VLANTIDX_VLAN_LEARN_DISABLED BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ANA_TABLES_VLANTIDX_VLAN_MIRROR BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ANA_TABLES_VLANTIDX_VLAN_SRC_CHK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ANA_TABLES_VLANTIDX_V_INDEX(x) ((x) & GENMASK(11, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ANA_TABLES_VLANTIDX_V_INDEX_M GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK(x) (((x) << 2) & GENMASK(8, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_M GENMASK(8, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_X(x) (((x) & GENMASK(8, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD_M GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ANA_TABLES_ISDXTIDX_ISDX_SDLBI(x) (((x) << 21) & GENMASK(28, 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_M GENMASK(28, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_X(x) (((x) & GENMASK(28, 21)) >> 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ANA_TABLES_ISDXTIDX_ISDX_MSTI(x) (((x) << 15) & GENMASK(20, 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ANA_TABLES_ISDXTIDX_ISDX_MSTI_M GENMASK(20, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ANA_TABLES_ISDXTIDX_ISDX_MSTI_X(x) (((x) & GENMASK(20, 15)) >> 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ANA_TABLES_ISDXTIDX_ISDX_ES0_KEY_ENA BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ANA_TABLES_ISDXTIDX_ISDX_FORCE_ENA BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ANA_TABLES_ISDXTIDX_ISDX_INDEX(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ANA_TABLES_ISDXTIDX_ISDX_INDEX_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ANA_TABLES_ENTRYLIM_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ANA_TABLES_ENTRYLIM_ENTRYLIM(x) (((x) << 14) & GENMASK(17, 14))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ANA_TABLES_ENTRYLIM_ENTRYLIM_M GENMASK(17, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ANA_TABLES_ENTRYLIM_ENTRYLIM_X(x) (((x) & GENMASK(17, 14)) >> 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ANA_TABLES_ENTRYLIM_ENTRYSTAT(x) ((x) & GENMASK(13, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ANA_TABLES_ENTRYLIM_ENTRYSTAT_M GENMASK(13, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM(x) (((x) << 4) & GENMASK(31, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_M GENMASK(31, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_X(x) (((x) & GENMASK(31, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ANA_TABLES_STREAMACCESS_SEQ_GEN_REC_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ANA_TABLES_STREAMACCESS_GEN_REC_TYPE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD_M GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS(x) (((x) << 30) & GENMASK(31, 30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_M GENMASK(31, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_X(x) (((x) & GENMASK(31, 30)) >> 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ANA_TABLES_STREAMTIDX_S_INDEX(x) (((x) << 16) & GENMASK(22, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ANA_TABLES_STREAMTIDX_S_INDEX_M GENMASK(22, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ANA_TABLES_STREAMTIDX_S_INDEX_X(x) (((x) & GENMASK(22, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ANA_TABLES_STREAMTIDX_FORCE_SF_BEHAVIOUR BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN(x) (((x) << 8) & GENMASK(13, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_M GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_X(x) (((x) & GENMASK(13, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ANA_TABLES_STREAMTIDX_RESET_ON_ROGUE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ANA_TABLES_STREAMTIDX_REDTAG_POP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ANA_TABLES_STREAMTIDX_STREAM_SPLIT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2(x) ((x) & GENMASK(4, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2_M GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ANA_TABLES_SEQ_MASK_SPLIT_MASK(x) (((x) << 16) & GENMASK(22, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ANA_TABLES_SEQ_MASK_SPLIT_MASK_M GENMASK(22, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ANA_TABLES_SEQ_MASK_SPLIT_MASK_X(x) (((x) & GENMASK(22, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK(x) ((x) & GENMASK(6, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK_M GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ANA_TABLES_SFID_MASK_IGR_PORT_MASK(x) (((x) << 1) & GENMASK(7, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_M GENMASK(7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_X(x) (((x) & GENMASK(7, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ANA_TABLES_SFIDACCESS_IGR_PRIO(x) (((x) << 19) & GENMASK(21, 19))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ANA_TABLES_SFIDACCESS_IGR_PRIO_M GENMASK(21, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ANA_TABLES_SFIDACCESS_IGR_PRIO_X(x) (((x) & GENMASK(21, 19)) >> 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ANA_TABLES_SFIDACCESS_FORCE_BLOCK BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(x) (((x) << 2) & GENMASK(17, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_M GENMASK(17, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_X(x) (((x) & GENMASK(17, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ANA_TABLES_SFIDTIDX_SGID_VALID BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ANA_TABLES_SFIDTIDX_SGID(x) (((x) << 18) & GENMASK(25, 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ANA_TABLES_SFIDTIDX_SGID_M GENMASK(25, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ANA_TABLES_SFIDTIDX_SGID_X(x) (((x) & GENMASK(25, 18)) >> 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ANA_TABLES_SFIDTIDX_POL_ENA BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ANA_TABLES_SFIDTIDX_POL_IDX(x) (((x) << 8) & GENMASK(16, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ANA_TABLES_SFIDTIDX_POL_IDX_M GENMASK(16, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ANA_TABLES_SFIDTIDX_POL_IDX_X(x) (((x) & GENMASK(16, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ANA_TABLES_SFIDTIDX_SFID_INDEX(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define ANA_TABLES_SFIDTIDX_SFID_INDEX_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define ANA_MSTI_STATE_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ANA_OAM_UPM_LM_CNT_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ANA_SG_ACCESS_CTRL_SGID(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ANA_SG_ACCESS_CTRL_SGID_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ANA_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ANA_SG_CONFIG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(18, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(18, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 21) & GENMASK(24, 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(24, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(24, 21)) >> 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define ANA_SG_GCL_GS_CONFIG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define ANA_SG_GCL_GS_CONFIG_IPS(x) ((x) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define ANA_SG_GCL_GS_CONFIG_IPS_M GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define ANA_SG_GCL_GS_CONFIG_GATE_STATE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ANA_SG_GCL_TI_CONFIG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define ANA_SG_STATUS_REG_3_GATE_STATE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ANA_SG_STATUS_REG_3_IPS(x) (((x) << 20) & GENMASK(23, 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ANA_SG_STATUS_REG_3_IPS_M GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define ANA_SG_STATUS_REG_3_IPS_X(x) (((x) & GENMASK(23, 20)) >> 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define ANA_SG_STATUS_REG_3_CONFIG_PENDING BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define ANA_PORT_VLAN_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define ANA_PORT_VLAN_CFG_VLAN_VID_AS_ISDX BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ANA_PORT_VLAN_CFG_VLAN_POP_CNT(x) (((x) << 18) & GENMASK(19, 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M GENMASK(19, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_X(x) (((x) & GENMASK(19, 18)) >> 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ANA_PORT_VLAN_CFG_VLAN_INNER_TAG_ENA BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define ANA_PORT_VLAN_CFG_VLAN_TAG_TYPE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ANA_PORT_VLAN_CFG_VLAN_DEI BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ANA_PORT_VLAN_CFG_VLAN_PCP(x) (((x) << 12) & GENMASK(14, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ANA_PORT_VLAN_CFG_VLAN_PCP_M GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ANA_PORT_VLAN_CFG_VLAN_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ANA_PORT_VLAN_CFG_VLAN_VID(x) ((x) & GENMASK(11, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ANA_PORT_VLAN_CFG_VLAN_VID_M GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ANA_PORT_DROP_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ANA_PORT_DROP_CFG_DROP_C_TAGGED_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define ANA_PORT_DROP_CFG_DROP_NULL_MAC_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define ANA_PORT_QOS_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define ANA_PORT_QOS_CFG_DP_DEFAULT_VAL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(x) (((x) << 5) & GENMASK(7, 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(x) (((x) & GENMASK(7, 5)) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define ANA_PORT_QOS_CFG_QOS_DSCP_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define ANA_PORT_QOS_CFG_QOS_PCP_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define ANA_PORT_QOS_CFG_DSCP_REWR_CFG(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define ANA_PORT_QOS_CFG_DSCP_REWR_CFG_M GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define ANA_PORT_VCAP_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define ANA_PORT_VCAP_CFG_S1_ENA BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA(x) (((x) << 11) & GENMASK(13, 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_M GENMASK(13, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_X(x) (((x) & GENMASK(13, 11)) >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA(x) (((x) << 8) & GENMASK(10, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_M GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_X(x) (((x) & GENMASK(10, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define ANA_PORT_VCAP_CFG_PAG_VAL(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define ANA_PORT_VCAP_CFG_PAG_VAL_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define ANA_PORT_VCAP_S1_KEY_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define ANA_PORT_VCAP_S1_KEY_CFG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG(x) (((x) << 4) & GENMASK(6, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_M GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_X(x) (((x) & GENMASK(6, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG(x) (((x) << 2) & GENMASK(3, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_M GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG_M GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define ANA_PORT_VCAP_S2_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA(x) (((x) << 17) & GENMASK(18, 17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_M GENMASK(18, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_X(x) (((x) & GENMASK(18, 17)) >> 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA(x) (((x) << 15) & GENMASK(16, 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_M GENMASK(16, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_X(x) (((x) & GENMASK(16, 15)) >> 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define ANA_PORT_VCAP_S2_CFG_S2_ENA BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(x) (((x) << 12) & GENMASK(13, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_M GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_X(x) (((x) & GENMASK(13, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(x) (((x) << 10) & GENMASK(11, 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_X(x) (((x) & GENMASK(11, 10)) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(x) (((x) << 8) & GENMASK(9, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_M GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_X(x) (((x) & GENMASK(9, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(x) (((x) << 6) & GENMASK(7, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_X(x) (((x) & GENMASK(7, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(x) (((x) << 2) & GENMASK(5, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_M GENMASK(5, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_X(x) (((x) & GENMASK(5, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS_M GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define ANA_PORT_PCP_DEI_MAP_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define ANA_PORT_PCP_DEI_MAP_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(x) ((x) & GENMASK(2, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define ANA_PORT_CPU_FWD_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define ANA_PORT_CPU_FWD_CFG_CPU_VRAP_REDIR_ENA BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define ANA_PORT_CPU_FWD_CFG_CPU_SRC_COPY_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_DROP_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_REDIR_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define ANA_PORT_CPU_FWD_CFG_CPU_OAM_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define ANA_PORT_CPU_FWD_BPDU_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_M GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define ANA_PORT_CPU_FWD_GARP_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_M GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define ANA_PORT_CPU_FWD_CCM_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_M GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define ANA_PORT_PORT_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define ANA_PORT_PORT_CFG_SRC_MIRROR_ENA BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define ANA_PORT_PORT_CFG_LIMIT_DROP BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define ANA_PORT_PORT_CFG_LIMIT_CPU BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_DROP BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_CPU BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define ANA_PORT_PORT_CFG_LEARNDROP BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define ANA_PORT_PORT_CFG_LEARNCPU BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define ANA_PORT_PORT_CFG_LEARNAUTO BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define ANA_PORT_PORT_CFG_LEARN_ENA BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define ANA_PORT_PORT_CFG_PORTID_VAL(x) (((x) << 2) & GENMASK(5, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define ANA_PORT_PORT_CFG_PORTID_VAL_M GENMASK(5, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define ANA_PORT_PORT_CFG_PORTID_VAL_X(x) (((x) & GENMASK(5, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define ANA_PORT_PORT_CFG_USE_B_DOM_TBL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define ANA_PORT_PORT_CFG_LSR_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define ANA_PORT_POL_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define ANA_PORT_POL_CFG_POL_CPU_REDIR_8021 BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define ANA_PORT_POL_CFG_POL_CPU_REDIR_IP BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define ANA_PORT_POL_CFG_PORT_POL_ENA BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define ANA_PORT_POL_CFG_QUEUE_POL_ENA(x) (((x) << 9) & GENMASK(16, 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define ANA_PORT_POL_CFG_QUEUE_POL_ENA_M GENMASK(16, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define ANA_PORT_POL_CFG_QUEUE_POL_ENA_X(x) (((x) & GENMASK(16, 9)) >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define ANA_PORT_POL_CFG_POL_ORDER(x) ((x) & GENMASK(8, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define ANA_PORT_POL_CFG_POL_ORDER_M GENMASK(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define ANA_PORT_PTP_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define ANA_PORT_PTP_CFG_PTP_BACKPLANE_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define ANA_PORT_PTP_DLY1_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define ANA_PORT_PTP_DLY2_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define ANA_PORT_SFID_CFG_GSZ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define ANA_PORT_SFID_CFG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define ANA_PORT_SFID_CFG_SFID_VALID BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define ANA_PORT_SFID_CFG_SFID(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define ANA_PORT_SFID_CFG_SFID_M GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define ANA_PFC_PFC_CFG_GSZ 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define ANA_PFC_PFC_CFG_RX_PFC_ENA(x) (((x) << 2) & GENMASK(9, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define ANA_PFC_PFC_CFG_RX_PFC_ENA_M GENMASK(9, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define ANA_PFC_PFC_CFG_RX_PFC_ENA_X(x) (((x) & GENMASK(9, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define ANA_PFC_PFC_CFG_FC_LINK_SPEED(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define ANA_PFC_PFC_CFG_FC_LINK_SPEED_M GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define ANA_PFC_PFC_TIMER_GSZ 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define ANA_PFC_PFC_TIMER_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define ANA_IPT_OAM_MEP_CFG_GSZ 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P(x) (((x) << 6) & GENMASK(10, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_M GENMASK(10, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_X(x) (((x) & GENMASK(10, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define ANA_IPT_OAM_MEP_CFG_MEP_IDX(x) (((x) << 1) & GENMASK(5, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_M GENMASK(5, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_X(x) (((x) & GENMASK(5, 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define ANA_IPT_IPT_GSZ 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define ANA_IPT_IPT_IPT_CFG(x) (((x) << 15) & GENMASK(16, 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define ANA_IPT_IPT_IPT_CFG_M GENMASK(16, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define ANA_IPT_IPT_IPT_CFG_X(x) (((x) & GENMASK(16, 15)) >> 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define ANA_IPT_IPT_ISDX_P(x) (((x) << 7) & GENMASK(14, 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define ANA_IPT_IPT_ISDX_P_M GENMASK(14, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define ANA_IPT_IPT_ISDX_P_X(x) (((x) & GENMASK(14, 7)) >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define ANA_IPT_IPT_PPT_IDX(x) ((x) & GENMASK(6, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define ANA_IPT_IPT_PPT_IDX_M GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define ANA_PPT_PPT_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define ANA_FID_MAP_FID_MAP_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define ANA_FID_MAP_FID_MAP_FID_C_VAL(x) (((x) << 6) & GENMASK(11, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define ANA_FID_MAP_FID_MAP_FID_C_VAL_M GENMASK(11, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define ANA_FID_MAP_FID_MAP_FID_C_VAL_X(x) (((x) & GENMASK(11, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define ANA_FID_MAP_FID_MAP_FID_B_VAL(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define ANA_FID_MAP_FID_MAP_FID_B_VAL_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define ANA_AGGR_CFG_AC_RND_ENA BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define ANA_AGGR_CFG_AC_DMAC_ENA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define ANA_AGGR_CFG_AC_SMAC_ENA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define ANA_AGGR_CFG_AC_ISDX_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define ANA_CPUQ_CFG_CPUQ_MLD(x) (((x) << 27) & GENMASK(29, 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define ANA_CPUQ_CFG_CPUQ_MLD_M GENMASK(29, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define ANA_CPUQ_CFG_CPUQ_MLD_X(x) (((x) & GENMASK(29, 27)) >> 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define ANA_CPUQ_CFG_CPUQ_IGMP(x) (((x) << 24) & GENMASK(26, 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define ANA_CPUQ_CFG_CPUQ_IGMP_M GENMASK(26, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define ANA_CPUQ_CFG_CPUQ_IGMP_X(x) (((x) & GENMASK(26, 24)) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(x) (((x) << 21) & GENMASK(23, 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_M GENMASK(23, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_X(x) (((x) & GENMASK(23, 21)) >> 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(x) (((x) << 18) & GENMASK(20, 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_M GENMASK(20, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_X(x) (((x) & GENMASK(20, 18)) >> 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(x) (((x) << 15) & GENMASK(17, 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_M GENMASK(17, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_X(x) (((x) & GENMASK(17, 15)) >> 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define ANA_CPUQ_CFG_CPUQ_SRC_COPY(x) (((x) << 12) & GENMASK(14, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define ANA_CPUQ_CFG_CPUQ_SRC_COPY_M GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define ANA_CPUQ_CFG_CPUQ_SRC_COPY_X(x) (((x) & GENMASK(14, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define ANA_CPUQ_CFG_CPUQ_MAC_COPY(x) (((x) << 9) & GENMASK(11, 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define ANA_CPUQ_CFG_CPUQ_MAC_COPY_M GENMASK(11, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define ANA_CPUQ_CFG_CPUQ_MAC_COPY_X(x) (((x) & GENMASK(11, 9)) >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define ANA_CPUQ_CFG_CPUQ_LRN(x) (((x) << 6) & GENMASK(8, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define ANA_CPUQ_CFG_CPUQ_LRN_M GENMASK(8, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define ANA_CPUQ_CFG_CPUQ_LRN_X(x) (((x) & GENMASK(8, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define ANA_CPUQ_CFG_CPUQ_MIRROR(x) (((x) << 3) & GENMASK(5, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define ANA_CPUQ_CFG_CPUQ_MIRROR_M GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define ANA_CPUQ_CFG_CPUQ_MIRROR_X(x) (((x) & GENMASK(5, 3)) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define ANA_CPUQ_CFG_CPUQ_SFLOW(x) ((x) & GENMASK(2, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define ANA_CPUQ_CFG_CPUQ_SFLOW_M GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define ANA_CPUQ_8021_CFG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(x) (((x) << 6) & GENMASK(8, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_M GENMASK(8, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_X(x) (((x) & GENMASK(8, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(x) (((x) << 3) & GENMASK(5, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_M GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_X(x) (((x) & GENMASK(5, 3)) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL(x) ((x) & GENMASK(2, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL_M GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define ANA_DSCP_CFG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define ANA_DSCP_CFG_QOS_DSCP_VAL(x) (((x) << 8) & GENMASK(10, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define ANA_DSCP_CFG_QOS_DSCP_VAL_M GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define ANA_DSCP_CFG_QOS_DSCP_VAL_X(x) (((x) & GENMASK(10, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL(x) (((x) << 2) & GENMASK(7, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_M GENMASK(7, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(x) (((x) & GENMASK(7, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define ANA_DSCP_REWR_CFG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define ANA_VCAP_RNG_TYPE_CFG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define ANA_VCAP_RNG_VAL_CFG_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL(x) (((x) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_M GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_X(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL_M GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define ANA_VRAP_CFG_VRAP_VLAN_AWARE_ENA BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define ANA_VRAP_CFG_VRAP_VID(x) ((x) & GENMASK(11, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define ANA_VRAP_CFG_VRAP_VID_M GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define ANA_DISCARD_CFG_DROP_TAGGING_ISDX0 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define ANA_DISCARD_CFG_DROP_CTRLPROT_ISDX0 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define ANA_DISCARD_CFG_DROP_TAGGING_S2_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define ANA_DISCARD_CFG_DROP_CTRLPROT_S2_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define ANA_FID_CFG_VID_MC_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define ANA_POL_PIR_CFG_GSZ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define ANA_POL_PIR_CFG_PIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define ANA_POL_PIR_CFG_PIR_RATE_M GENMASK(20, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define ANA_POL_PIR_CFG_PIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define ANA_POL_PIR_CFG_PIR_BURST(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define ANA_POL_PIR_CFG_PIR_BURST_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define ANA_POL_CIR_CFG_GSZ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define ANA_POL_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define ANA_POL_CIR_CFG_CIR_RATE_M GENMASK(20, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define ANA_POL_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define ANA_POL_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define ANA_POL_CIR_CFG_CIR_BURST_M GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define ANA_POL_MODE_CFG_GSZ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define ANA_POL_MODE_CFG_IPG_SIZE(x) (((x) << 5) & GENMASK(9, 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define ANA_POL_MODE_CFG_IPG_SIZE_M GENMASK(9, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define ANA_POL_MODE_CFG_IPG_SIZE_X(x) (((x) & GENMASK(9, 5)) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define ANA_POL_MODE_CFG_FRM_MODE(x) (((x) << 3) & GENMASK(4, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define ANA_POL_MODE_CFG_FRM_MODE_M GENMASK(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define ANA_POL_MODE_CFG_FRM_MODE_X(x) (((x) & GENMASK(4, 3)) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define ANA_POL_MODE_CFG_DLB_COUPLED BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define ANA_POL_MODE_CFG_CIR_ENA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define ANA_POL_MODE_CFG_OVERSHOOT_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define ANA_POL_PIR_STATE_GSZ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define ANA_POL_CIR_STATE_GSZ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define ANA_POL_STATE_GSZ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define ANA_POL_FLOWC_RSZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define ANA_POL_FLOWC_POL_FLOWC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define ANA_POL_HYST_POL_FC_HYST(x) (((x) << 4) & GENMASK(9, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define ANA_POL_HYST_POL_FC_HYST_M GENMASK(9, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define ANA_POL_HYST_POL_FC_HYST_X(x) (((x) & GENMASK(9, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define ANA_POL_HYST_POL_STOP_HYST(x) ((x) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define ANA_POL_HYST_POL_STOP_HYST_M GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define ANA_POL_MISC_CFG_POL_CLOSE_ALL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define ANA_POL_MISC_CFG_POL_LEAK_DIS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags