^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2014-2016 Freescale Semiconductor Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2016 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __FSL_DPAA2_FD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __FSL_DPAA2_FD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * DOC: DPAA2 FD - Frame Descriptor APIs for DPAA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Frame Descriptors (FDs) are used to describe frame data in the DPAA2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Frames can be enqueued and dequeued to Frame Queues (FQs) which are consumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * by the various DPAA accelerators (WRIOP, SEC, PME, DCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * There are three types of frames: single, scatter gather, and frame lists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * The set of APIs in this file must be used to create, manipulate and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * query Frame Descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * struct dpaa2_fd - Struct describing FDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @words: for easier/faster copying the whole FD structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @addr: address in the FD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @len: length in the FD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @bpid: buffer pool ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @format_offset: format, offset, and short-length fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @frc: frame context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @ctrl: control bits...including dd, sc, va, err, etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @flc: flow context address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * This structure represents the basic Frame Descriptor used in the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct dpaa2_fd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 words[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct dpaa2_fd_simple {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) __le64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) __le32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) __le16 bpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __le16 format_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __le32 frc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __le32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __le64 flc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) } simple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FD_SHORT_LEN_FLAG_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FD_SHORT_LEN_FLAG_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FD_SHORT_LEN_MASK 0x3FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FD_OFFSET_MASK 0x0FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FD_FORMAT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FD_FORMAT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FD_BPID_MASK 0x3FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SG_SHORT_LEN_FLAG_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SG_SHORT_LEN_FLAG_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SG_SHORT_LEN_MASK 0x1FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SG_OFFSET_MASK 0x0FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SG_FORMAT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SG_FORMAT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SG_BPID_MASK 0x3FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SG_FINAL_FLAG_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SG_FINAL_FLAG_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FL_SHORT_LEN_FLAG_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FL_SHORT_LEN_FLAG_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FL_SHORT_LEN_MASK 0x3FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define FL_OFFSET_MASK 0x0FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FL_FORMAT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FL_FORMAT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FL_BPID_MASK 0x3FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FL_FINAL_FLAG_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FL_FINAL_FLAG_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Error bits in FD CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FD_CTRL_ERR_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define FD_CTRL_UFD 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define FD_CTRL_SBE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define FD_CTRL_FLC 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define FD_CTRL_FSE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define FD_CTRL_FAERR 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Annotation bits in FD CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define FD_CTRL_PTA 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define FD_CTRL_PTV1 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enum dpaa2_fd_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dpaa2_fd_single = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dpaa2_fd_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dpaa2_fd_sg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * dpaa2_fd_get_addr() - get the addr field of frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Return the address in the frame descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline dma_addr_t dpaa2_fd_get_addr(const struct dpaa2_fd *fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return (dma_addr_t)le64_to_cpu(fd->simple.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * dpaa2_fd_set_addr() - Set the addr field of frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @addr: the address needs to be set in frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline void dpaa2_fd_set_addr(struct dpaa2_fd *fd, dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) fd->simple.addr = cpu_to_le64(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * dpaa2_fd_get_frc() - Get the frame context in the frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Return the frame context field in the frame descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static inline u32 dpaa2_fd_get_frc(const struct dpaa2_fd *fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return le32_to_cpu(fd->simple.frc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * dpaa2_fd_set_frc() - Set the frame context in the frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @frc: the frame context needs to be set in frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline void dpaa2_fd_set_frc(struct dpaa2_fd *fd, u32 frc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) fd->simple.frc = cpu_to_le32(frc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * dpaa2_fd_get_ctrl() - Get the control bits in the frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Return the control bits field in the frame descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline u32 dpaa2_fd_get_ctrl(const struct dpaa2_fd *fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return le32_to_cpu(fd->simple.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * dpaa2_fd_set_ctrl() - Set the control bits in the frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @ctrl: the control bits to be set in the frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static inline void dpaa2_fd_set_ctrl(struct dpaa2_fd *fd, u32 ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) fd->simple.ctrl = cpu_to_le32(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * dpaa2_fd_get_flc() - Get the flow context in the frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Return the flow context in the frame descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static inline dma_addr_t dpaa2_fd_get_flc(const struct dpaa2_fd *fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return (dma_addr_t)le64_to_cpu(fd->simple.flc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * dpaa2_fd_set_flc() - Set the flow context field of frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @flc_addr: the flow context needs to be set in frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static inline void dpaa2_fd_set_flc(struct dpaa2_fd *fd, dma_addr_t flc_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) fd->simple.flc = cpu_to_le64(flc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline bool dpaa2_fd_short_len(const struct dpaa2_fd *fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return !!((le16_to_cpu(fd->simple.format_offset) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) FD_SHORT_LEN_FLAG_SHIFT) & FD_SHORT_LEN_FLAG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * dpaa2_fd_get_len() - Get the length in the frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Return the length field in the frame descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static inline u32 dpaa2_fd_get_len(const struct dpaa2_fd *fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (dpaa2_fd_short_len(fd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return le32_to_cpu(fd->simple.len) & FD_SHORT_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return le32_to_cpu(fd->simple.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * dpaa2_fd_set_len() - Set the length field of frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @len: the length needs to be set in frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static inline void dpaa2_fd_set_len(struct dpaa2_fd *fd, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) fd->simple.len = cpu_to_le32(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * dpaa2_fd_get_offset() - Get the offset field in the frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Return the offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static inline uint16_t dpaa2_fd_get_offset(const struct dpaa2_fd *fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return le16_to_cpu(fd->simple.format_offset) & FD_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * dpaa2_fd_set_offset() - Set the offset field of frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @offset: the offset needs to be set in frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static inline void dpaa2_fd_set_offset(struct dpaa2_fd *fd, uint16_t offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) fd->simple.format_offset &= cpu_to_le16(~FD_OFFSET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) fd->simple.format_offset |= cpu_to_le16(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * dpaa2_fd_get_format() - Get the format field in the frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Return the format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static inline enum dpaa2_fd_format dpaa2_fd_get_format(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) const struct dpaa2_fd *fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return (enum dpaa2_fd_format)((le16_to_cpu(fd->simple.format_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) >> FD_FORMAT_SHIFT) & FD_FORMAT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * dpaa2_fd_set_format() - Set the format field of frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * @format: the format needs to be set in frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static inline void dpaa2_fd_set_format(struct dpaa2_fd *fd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) enum dpaa2_fd_format format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) fd->simple.format_offset &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) cpu_to_le16(~(FD_FORMAT_MASK << FD_FORMAT_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) fd->simple.format_offset |= cpu_to_le16(format << FD_FORMAT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * dpaa2_fd_get_bpid() - Get the bpid field in the frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * Return the buffer pool id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static inline uint16_t dpaa2_fd_get_bpid(const struct dpaa2_fd *fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return le16_to_cpu(fd->simple.bpid) & FD_BPID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * dpaa2_fd_set_bpid() - Set the bpid field of frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * @fd: the given frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @bpid: buffer pool id to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static inline void dpaa2_fd_set_bpid(struct dpaa2_fd *fd, uint16_t bpid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) fd->simple.bpid &= cpu_to_le16(~(FD_BPID_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) fd->simple.bpid |= cpu_to_le16(bpid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * struct dpaa2_sg_entry - the scatter-gathering structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * @addr: address of the sg entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * @len: length in this sg entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * @bpid: buffer pool id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * @format_offset: format and offset fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct dpaa2_sg_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) __le64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) __le32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __le16 bpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) __le16 format_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) enum dpaa2_sg_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dpaa2_sg_single = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dpaa2_sg_frame_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dpaa2_sg_sgt_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Accessors for SG entry fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * dpaa2_sg_get_addr() - Get the address from SG entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * @sg: the given scatter-gathering object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Return the address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static inline dma_addr_t dpaa2_sg_get_addr(const struct dpaa2_sg_entry *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return (dma_addr_t)le64_to_cpu(sg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * dpaa2_sg_set_addr() - Set the address in SG entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * @sg: the given scatter-gathering object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * @addr: the address to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static inline void dpaa2_sg_set_addr(struct dpaa2_sg_entry *sg, dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) sg->addr = cpu_to_le64(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static inline bool dpaa2_sg_short_len(const struct dpaa2_sg_entry *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return !!((le16_to_cpu(sg->format_offset) >> SG_SHORT_LEN_FLAG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) & SG_SHORT_LEN_FLAG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * dpaa2_sg_get_len() - Get the length in SG entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * @sg: the given scatter-gathering object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Return the length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static inline u32 dpaa2_sg_get_len(const struct dpaa2_sg_entry *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (dpaa2_sg_short_len(sg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return le32_to_cpu(sg->len) & SG_SHORT_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return le32_to_cpu(sg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * dpaa2_sg_set_len() - Set the length in SG entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @sg: the given scatter-gathering object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @len: the length to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static inline void dpaa2_sg_set_len(struct dpaa2_sg_entry *sg, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) sg->len = cpu_to_le32(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * dpaa2_sg_get_offset() - Get the offset in SG entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * @sg: the given scatter-gathering object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Return the offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static inline u16 dpaa2_sg_get_offset(const struct dpaa2_sg_entry *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return le16_to_cpu(sg->format_offset) & SG_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * dpaa2_sg_set_offset() - Set the offset in SG entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * @sg: the given scatter-gathering object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * @offset: the offset to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static inline void dpaa2_sg_set_offset(struct dpaa2_sg_entry *sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) sg->format_offset &= cpu_to_le16(~SG_OFFSET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) sg->format_offset |= cpu_to_le16(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * dpaa2_sg_get_format() - Get the SG format in SG entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * @sg: the given scatter-gathering object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * Return the format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static inline enum dpaa2_sg_format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dpaa2_sg_get_format(const struct dpaa2_sg_entry *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return (enum dpaa2_sg_format)((le16_to_cpu(sg->format_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) >> SG_FORMAT_SHIFT) & SG_FORMAT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * dpaa2_sg_set_format() - Set the SG format in SG entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * @sg: the given scatter-gathering object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * @format: the format to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static inline void dpaa2_sg_set_format(struct dpaa2_sg_entry *sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) enum dpaa2_sg_format format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) sg->format_offset &= cpu_to_le16(~(SG_FORMAT_MASK << SG_FORMAT_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) sg->format_offset |= cpu_to_le16(format << SG_FORMAT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * dpaa2_sg_get_bpid() - Get the buffer pool id in SG entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * @sg: the given scatter-gathering object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * Return the bpid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static inline u16 dpaa2_sg_get_bpid(const struct dpaa2_sg_entry *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return le16_to_cpu(sg->bpid) & SG_BPID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * dpaa2_sg_set_bpid() - Set the buffer pool id in SG entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * @sg: the given scatter-gathering object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * @bpid: the bpid to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static inline void dpaa2_sg_set_bpid(struct dpaa2_sg_entry *sg, u16 bpid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) sg->bpid &= cpu_to_le16(~(SG_BPID_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) sg->bpid |= cpu_to_le16(bpid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * dpaa2_sg_is_final() - Check final bit in SG entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * @sg: the given scatter-gathering object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * Return bool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static inline bool dpaa2_sg_is_final(const struct dpaa2_sg_entry *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return !!(le16_to_cpu(sg->format_offset) >> SG_FINAL_FLAG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * dpaa2_sg_set_final() - Set the final bit in SG entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @sg: the given scatter-gathering object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * @final: the final boolean to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static inline void dpaa2_sg_set_final(struct dpaa2_sg_entry *sg, bool final)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) sg->format_offset &= cpu_to_le16((~(SG_FINAL_FLAG_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) << SG_FINAL_FLAG_SHIFT)) & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) sg->format_offset |= cpu_to_le16(final << SG_FINAL_FLAG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * struct dpaa2_fl_entry - structure for frame list entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * @addr: address in the FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * @len: length in the FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * @bpid: buffer pool ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * @format_offset: format, offset, and short-length fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * @frc: frame context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * @ctrl: control bits...including pta, pvt1, pvt2, err, etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * @flc: flow context address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct dpaa2_fl_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) __le64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __le32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) __le16 bpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) __le16 format_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) __le32 frc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) __le32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) __le64 flc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) enum dpaa2_fl_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dpaa2_fl_single = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dpaa2_fl_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dpaa2_fl_sg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * dpaa2_fl_get_addr() - get the addr field of FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * Return the address in the frame list entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static inline dma_addr_t dpaa2_fl_get_addr(const struct dpaa2_fl_entry *fle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return (dma_addr_t)le64_to_cpu(fle->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * dpaa2_fl_set_addr() - Set the addr field of FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * @addr: the address needs to be set in frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static inline void dpaa2_fl_set_addr(struct dpaa2_fl_entry *fle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) fle->addr = cpu_to_le64(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * dpaa2_fl_get_frc() - Get the frame context in the FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * Return the frame context field in the frame lsit entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static inline u32 dpaa2_fl_get_frc(const struct dpaa2_fl_entry *fle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return le32_to_cpu(fle->frc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * dpaa2_fl_set_frc() - Set the frame context in the FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * @frc: the frame context needs to be set in frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static inline void dpaa2_fl_set_frc(struct dpaa2_fl_entry *fle, u32 frc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) fle->frc = cpu_to_le32(frc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * dpaa2_fl_get_ctrl() - Get the control bits in the FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * Return the control bits field in the frame list entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static inline u32 dpaa2_fl_get_ctrl(const struct dpaa2_fl_entry *fle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return le32_to_cpu(fle->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * dpaa2_fl_set_ctrl() - Set the control bits in the FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * @ctrl: the control bits to be set in the frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static inline void dpaa2_fl_set_ctrl(struct dpaa2_fl_entry *fle, u32 ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) fle->ctrl = cpu_to_le32(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * dpaa2_fl_get_flc() - Get the flow context in the FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * Return the flow context in the frame list entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static inline dma_addr_t dpaa2_fl_get_flc(const struct dpaa2_fl_entry *fle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return (dma_addr_t)le64_to_cpu(fle->flc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * dpaa2_fl_set_flc() - Set the flow context field of FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * @flc_addr: the flow context needs to be set in frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static inline void dpaa2_fl_set_flc(struct dpaa2_fl_entry *fle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dma_addr_t flc_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) fle->flc = cpu_to_le64(flc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static inline bool dpaa2_fl_short_len(const struct dpaa2_fl_entry *fle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return !!((le16_to_cpu(fle->format_offset) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) FL_SHORT_LEN_FLAG_SHIFT) & FL_SHORT_LEN_FLAG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * dpaa2_fl_get_len() - Get the length in the FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * Return the length field in the frame list entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static inline u32 dpaa2_fl_get_len(const struct dpaa2_fl_entry *fle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (dpaa2_fl_short_len(fle))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return le32_to_cpu(fle->len) & FL_SHORT_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return le32_to_cpu(fle->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * dpaa2_fl_set_len() - Set the length field of FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * @len: the length needs to be set in frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static inline void dpaa2_fl_set_len(struct dpaa2_fl_entry *fle, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) fle->len = cpu_to_le32(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * dpaa2_fl_get_offset() - Get the offset field in the frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * Return the offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static inline u16 dpaa2_fl_get_offset(const struct dpaa2_fl_entry *fle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return le16_to_cpu(fle->format_offset) & FL_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * dpaa2_fl_set_offset() - Set the offset field of FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * @offset: the offset needs to be set in frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static inline void dpaa2_fl_set_offset(struct dpaa2_fl_entry *fle, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) fle->format_offset &= cpu_to_le16(~FL_OFFSET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) fle->format_offset |= cpu_to_le16(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * dpaa2_fl_get_format() - Get the format field in the FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * Return the format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static inline enum dpaa2_fl_format dpaa2_fl_get_format(const struct dpaa2_fl_entry *fle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return (enum dpaa2_fl_format)((le16_to_cpu(fle->format_offset) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) FL_FORMAT_SHIFT) & FL_FORMAT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * dpaa2_fl_set_format() - Set the format field of FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * @format: the format needs to be set in frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static inline void dpaa2_fl_set_format(struct dpaa2_fl_entry *fle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) enum dpaa2_fl_format format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) fle->format_offset &= cpu_to_le16(~(FL_FORMAT_MASK << FL_FORMAT_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) fle->format_offset |= cpu_to_le16(format << FL_FORMAT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * dpaa2_fl_get_bpid() - Get the bpid field in the FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * Return the buffer pool id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static inline u16 dpaa2_fl_get_bpid(const struct dpaa2_fl_entry *fle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return le16_to_cpu(fle->bpid) & FL_BPID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * dpaa2_fl_set_bpid() - Set the bpid field of FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * @bpid: buffer pool id to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static inline void dpaa2_fl_set_bpid(struct dpaa2_fl_entry *fle, u16 bpid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) fle->bpid &= cpu_to_le16(~(FL_BPID_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) fle->bpid |= cpu_to_le16(bpid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * dpaa2_fl_is_final() - Check final bit in FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * Return bool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static inline bool dpaa2_fl_is_final(const struct dpaa2_fl_entry *fle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return !!(le16_to_cpu(fle->format_offset) >> FL_FINAL_FLAG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * dpaa2_fl_set_final() - Set the final bit in FLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * @fle: the given frame list entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * @final: the final boolean to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static inline void dpaa2_fl_set_final(struct dpaa2_fl_entry *fle, bool final)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) fle->format_offset &= cpu_to_le16((~(FL_FINAL_FLAG_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) FL_FINAL_FLAG_SHIFT)) & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) fle->format_offset |= cpu_to_le16(final << FL_FINAL_FLAG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #endif /* __FSL_DPAA2_FD_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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