^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __CPM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __CPM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <soc/fsl/qe/qe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * SPI Parameter RAM common to QE and CPM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct spi_pram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) __be16 rbase; /* Rx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) __be16 tbase; /* Tx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u8 rfcr; /* Rx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u8 tfcr; /* Tx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) __be16 mrblr; /* Max receive buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) __be32 rstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) __be32 rdp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) __be16 rbptr; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) __be16 rbc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) __be32 rxtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) __be32 tstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) __be32 tdp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) __be16 tbptr; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) __be16 tbc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) __be32 txtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __be32 res; /* Tx temp. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) __be16 rpbase; /* Relocation pointer (CPM1 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __be16 res1; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * USB Controller pram common to QE and CPM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct usb_ctlr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 usb_usmod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 usb_usadr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 usb_uscom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 res1[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) __be16 usb_usep[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 res2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __be16 usb_usber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 res3[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __be16 usb_usbmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 res4[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 usb_usbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Fields down below are QE-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __be16 usb_ussft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 res5[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) __be16 usb_usfrn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 res6[0x22];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Function code bits, usually generic to devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #ifdef CONFIG_CPM1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Opcodes common to CPM1 and CPM2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CPM_CR_INIT_TRX ((ushort)0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CPM_CR_INIT_RX ((ushort)0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CPM_CR_INIT_TX ((ushort)0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CPM_CR_HUNT_MODE ((ushort)0x0003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CPM_CR_STOP_TX ((ushort)0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CPM_CR_RESTART_TX ((ushort)0x0006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CPM_CR_SET_GADDR ((ushort)0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CPM_CR_SET_TIMER ((ushort)0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CPM_CR_STOP_IDMA ((ushort)0x000b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Buffer descriptors used by many of the CPM protocols. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) typedef struct cpm_buf_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ushort cbd_sc; /* Status and Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ushort cbd_datlen; /* Data length in buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) uint cbd_bufaddr; /* Buffer address in host memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } cbd_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Buffer descriptor control/status used by serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BD_SC_EMPTY (0x8000) /* Receive is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BD_SC_READY (0x8000) /* Transmit is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BD_SC_INTRPT (0x1000) /* Interrupt on change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BD_SC_LAST (0x0800) /* Last buffer in frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BD_SC_TC (0x0400) /* Transmit CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BD_SC_CM (0x0200) /* Continuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BD_SC_ID (0x0100) /* Rec'd too many idles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BD_SC_P (0x0100) /* xmt preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BD_SC_BR (0x0020) /* Break received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BD_SC_FR (0x0010) /* Framing error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BD_SC_PR (0x0008) /* Parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BD_SC_NAK (0x0004) /* NAK - did not respond */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BD_SC_OV (0x0002) /* Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BD_SC_UN (0x0002) /* Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BD_SC_CD (0x0001) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BD_SC_CL (0x0001) /* Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Buffer descriptor control/status used by Ethernet receive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Common to SCC and FCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BD_ENET_RX_EMPTY (0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BD_ENET_RX_WRAP (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define BD_ENET_RX_INTR (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BD_ENET_RX_LAST (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BD_ENET_RX_FIRST (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BD_ENET_RX_MISS (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BD_ENET_RX_BC (0x0080) /* FCC Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BD_ENET_RX_MC (0x0040) /* FCC Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BD_ENET_RX_LG (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BD_ENET_RX_NO (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BD_ENET_RX_SH (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BD_ENET_RX_CR (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BD_ENET_RX_OV (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BD_ENET_RX_CL (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BD_ENET_RX_STATS (0x01ff) /* All status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Buffer descriptor control/status used by Ethernet transmit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Common to SCC and FCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BD_ENET_TX_READY (0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define BD_ENET_TX_PAD (0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BD_ENET_TX_WRAP (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define BD_ENET_TX_INTR (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define BD_ENET_TX_LAST (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define BD_ENET_TX_TC (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define BD_ENET_TX_DEF (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define BD_ENET_TX_HB (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define BD_ENET_TX_LC (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define BD_ENET_TX_RL (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define BD_ENET_TX_RCMASK (0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BD_ENET_TX_UN (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BD_ENET_TX_CSL (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BD_ENET_TX_STATS (0x03ff) /* All status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Buffer descriptor control/status used by Transparent mode SCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define BD_SCC_TX_LAST (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Buffer descriptor control/status used by I2C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define BD_I2C_START (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #ifdef CONFIG_CPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int cpm_command(u32 command, u8 opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static inline int cpm_command(u32 command, u8 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif /* CONFIG_CPM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int cpm2_gpiochip_add32(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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