Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Timer/Counter Unit (TC) registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef __SOC_ATMEL_TCB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define __SOC_ATMEL_TCB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * three general-purpose 16-bit timers.  These timers share one register bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * Depending on the SOC, each timer may have its own clock and IRQ, or those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * may be shared by the whole TC block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * These TC blocks may have up to nine external pins:  TCLK0..2 signals for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * or triggering.  Those pins need to be set up for use with the TC block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * else they will be used as GPIOs or for a different controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Although we expect each TC block to have a platform_device node, those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * nodes are not what drivers bind to.  Instead, they ask for a specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * TC block, by number ... which is a common approach on systems with many
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * timers.  Then they use clk_get() and platform_get_irq() to get clock and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * IRQ resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) struct clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * struct atmel_tcb_config - SoC data for a Timer/Counter Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * @counter_width: size in bits of a timer counter register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * @has_gclk: boolean indicating if a timer counter has a generic clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * @has_qdec: boolean indicating if a timer counter has a quadrature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * decoder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) struct atmel_tcb_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	size_t	counter_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	bool    has_gclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	bool    has_qdec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * struct atmel_tc - information about a Timer/Counter Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * @pdev: physical device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * @regs: mapping through which the I/O registers can be accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * @id: block id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * @tcb_config: configuration data from SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * @irq: irq for each of the three channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * @clk: internal clock source for each of the three channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * @node: list node, for tclib internal use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * @allocated: if already used, for tclib internal use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * On some platforms, each TC channel has its own clocks and IRQs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * while on others, all TC channels share the same clock and IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * Drivers should clk_enable() all the clocks they need even though
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * all the entries in @clk may point to the same physical clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * Likewise, drivers should request irqs independently for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * channel, but they must use IRQF_SHARED in case some of the entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * in @irq are actually the same IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) struct atmel_tc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct platform_device	*pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	void __iomem		*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	int                     id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	const struct atmel_tcb_config *tcb_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	int			irq[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct clk		*clk[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct clk		*slow_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct list_head	node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	bool			allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) extern struct atmel_tc *atmel_tc_alloc(unsigned block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) extern void atmel_tc_free(struct atmel_tc *tc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) extern const u8 atmel_tc_divisors[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * Two registers have block-wide controls.  These are: configuring the three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * "external" clocks (or event sources) used by the timer channels; and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * synchronizing the timers by resetting them all at once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  * "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * signals.  Or, it can mean "external to timer", using the TIOA output from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * one of the other two timers that's being run in waveform mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define ATMEL_TC_BCR	0xc0		/* TC Block Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define     ATMEL_TC_SYNC	(1 << 0)	/* synchronize timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ATMEL_TC_BMR	0xc4		/* TC Block Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define     ATMEL_TC_TC0XC0S	(3 << 0)	/* external clock 0 source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define        ATMEL_TC_TC0XC0S_TCLK0	(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define        ATMEL_TC_TC0XC0S_NONE	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define        ATMEL_TC_TC0XC0S_TIOA1	(2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define        ATMEL_TC_TC0XC0S_TIOA2	(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define     ATMEL_TC_TC1XC1S	(3 << 2)	/* external clock 1 source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define        ATMEL_TC_TC1XC1S_TCLK1	(0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define        ATMEL_TC_TC1XC1S_NONE	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define        ATMEL_TC_TC1XC1S_TIOA0	(2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define        ATMEL_TC_TC1XC1S_TIOA2	(3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define     ATMEL_TC_TC2XC2S	(3 << 4)	/* external clock 2 source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define        ATMEL_TC_TC2XC2S_TCLK2	(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define        ATMEL_TC_TC2XC2S_NONE	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define        ATMEL_TC_TC2XC2S_TIOA0	(2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define        ATMEL_TC_TC2XC2S_TIOA1	(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  * Each TC block has three "channels", each with one counter and controls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * when it's not "external") is silicon-specific.  AT91 platforms use one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * set of definitions; AVR32 platforms use a different set.  Don't hard-wire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * such knowledge into your code, use the global "atmel_tc_divisors" ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * where index N is the divisor for clock N+1, else zero to indicate it uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * the 32 KiHz clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * The timers can be chained in various ways, and operated in "waveform"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * generation mode (including PWM) or "capture" mode (to time events).  In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * both modes, behavior can be configured in many ways.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * Each timer has two I/O pins, TIOA and TIOB.  Waveform mode uses TIOA as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * PWM output, and TIOB as either another PWM or as a trigger.  Capture mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * uses them only as inputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ATMEL_TC_CHAN(idx)	((idx)*0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ATMEL_TC_REG(idx, reg)	(ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ATMEL_TC_CCR	0x00		/* Channel Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define     ATMEL_TC_CLKEN	(1 << 0)	/* clock enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define     ATMEL_TC_CLKDIS	(1 << 1)	/* clock disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define     ATMEL_TC_SWTRG	(1 << 2)	/* software trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ATMEL_TC_CMR	0x04		/* Channel Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Both modes share some CMR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define     ATMEL_TC_TCCLKS	(7 << 0)	/* clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define        ATMEL_TC_TIMER_CLOCK1	(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define        ATMEL_TC_TIMER_CLOCK2	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define        ATMEL_TC_TIMER_CLOCK3	(2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define        ATMEL_TC_TIMER_CLOCK4	(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define        ATMEL_TC_TIMER_CLOCK5	(4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define        ATMEL_TC_XC0		(5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define        ATMEL_TC_XC1		(6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define        ATMEL_TC_XC2		(7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define     ATMEL_TC_CLKI	(1 << 3)	/* clock invert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define     ATMEL_TC_BURST	(3 << 4)	/* clock gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define        ATMEL_TC_GATE_NONE	(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define        ATMEL_TC_GATE_XC0	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define        ATMEL_TC_GATE_XC1	(2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define        ATMEL_TC_GATE_XC2	(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define     ATMEL_TC_WAVE	(1 << 15)	/* true = Waveform mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* CAPTURE mode CMR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define     ATMEL_TC_LDBSTOP	(1 << 6)	/* counter stops on RB load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define     ATMEL_TC_LDBDIS	(1 << 7)	/* counter disable on RB load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define     ATMEL_TC_ETRGEDG	(3 << 8)	/* external trigger edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define        ATMEL_TC_ETRGEDG_NONE	(0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define        ATMEL_TC_ETRGEDG_RISING	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define        ATMEL_TC_ETRGEDG_FALLING	(2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define        ATMEL_TC_ETRGEDG_BOTH	(3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define     ATMEL_TC_ABETRG	(1 << 10)	/* external trigger is TIOA? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define     ATMEL_TC_CPCTRG	(1 << 14)	/* RC compare trigger enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define     ATMEL_TC_LDRA	(3 << 16)	/* RA loading edge (of TIOA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define        ATMEL_TC_LDRA_NONE	(0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define        ATMEL_TC_LDRA_RISING	(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define        ATMEL_TC_LDRA_FALLING	(2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define        ATMEL_TC_LDRA_BOTH	(3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define     ATMEL_TC_LDRB	(3 << 18)	/* RB loading edge (of TIOA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define        ATMEL_TC_LDRB_NONE	(0 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define        ATMEL_TC_LDRB_RISING	(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define        ATMEL_TC_LDRB_FALLING	(2 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define        ATMEL_TC_LDRB_BOTH	(3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* WAVEFORM mode CMR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define     ATMEL_TC_CPCSTOP	(1 <<  6)	/* RC compare stops counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define     ATMEL_TC_CPCDIS	(1 <<  7)	/* RC compare disables counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define     ATMEL_TC_EEVTEDG	(3 <<  8)	/* external event edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define        ATMEL_TC_EEVTEDG_NONE	(0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define        ATMEL_TC_EEVTEDG_RISING	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define        ATMEL_TC_EEVTEDG_FALLING	(2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define        ATMEL_TC_EEVTEDG_BOTH	(3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define     ATMEL_TC_EEVT	(3 << 10)	/* external event source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define        ATMEL_TC_EEVT_TIOB	(0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define        ATMEL_TC_EEVT_XC0	(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define        ATMEL_TC_EEVT_XC1	(2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define        ATMEL_TC_EEVT_XC2	(3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define     ATMEL_TC_ENETRG	(1 << 12)	/* external event is trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define     ATMEL_TC_WAVESEL	(3 << 13)	/* waveform type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define        ATMEL_TC_WAVESEL_UP	(0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define        ATMEL_TC_WAVESEL_UPDOWN	(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define        ATMEL_TC_WAVESEL_UP_AUTO	(2 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define        ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define     ATMEL_TC_ACPA	(3 << 16)	/* RA compare changes TIOA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define        ATMEL_TC_ACPA_NONE	(0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define        ATMEL_TC_ACPA_SET	(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define        ATMEL_TC_ACPA_CLEAR	(2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define        ATMEL_TC_ACPA_TOGGLE	(3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define     ATMEL_TC_ACPC	(3 << 18)	/* RC compare changes TIOA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define        ATMEL_TC_ACPC_NONE	(0 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define        ATMEL_TC_ACPC_SET	(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define        ATMEL_TC_ACPC_CLEAR	(2 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define        ATMEL_TC_ACPC_TOGGLE	(3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define     ATMEL_TC_AEEVT	(3 << 20)	/* external event changes TIOA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define        ATMEL_TC_AEEVT_NONE	(0 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define        ATMEL_TC_AEEVT_SET	(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define        ATMEL_TC_AEEVT_CLEAR	(2 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define        ATMEL_TC_AEEVT_TOGGLE	(3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define     ATMEL_TC_ASWTRG	(3 << 22)	/* software trigger changes TIOA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define        ATMEL_TC_ASWTRG_NONE	(0 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define        ATMEL_TC_ASWTRG_SET	(1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define        ATMEL_TC_ASWTRG_CLEAR	(2 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define        ATMEL_TC_ASWTRG_TOGGLE	(3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define     ATMEL_TC_BCPB	(3 << 24)	/* RB compare changes TIOB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define        ATMEL_TC_BCPB_NONE	(0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define        ATMEL_TC_BCPB_SET	(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define        ATMEL_TC_BCPB_CLEAR	(2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define        ATMEL_TC_BCPB_TOGGLE	(3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define     ATMEL_TC_BCPC	(3 << 26)	/* RC compare changes TIOB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define        ATMEL_TC_BCPC_NONE	(0 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define        ATMEL_TC_BCPC_SET	(1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define        ATMEL_TC_BCPC_CLEAR	(2 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define        ATMEL_TC_BCPC_TOGGLE	(3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define     ATMEL_TC_BEEVT	(3 << 28)	/* external event changes TIOB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define        ATMEL_TC_BEEVT_NONE	(0 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define        ATMEL_TC_BEEVT_SET	(1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define        ATMEL_TC_BEEVT_CLEAR	(2 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define        ATMEL_TC_BEEVT_TOGGLE	(3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define     ATMEL_TC_BSWTRG	(3 << 30)	/* software trigger changes TIOB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define        ATMEL_TC_BSWTRG_NONE	(0 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define        ATMEL_TC_BSWTRG_SET	(1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define        ATMEL_TC_BSWTRG_CLEAR	(2 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define        ATMEL_TC_BSWTRG_TOGGLE	(3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ATMEL_TC_CV	0x10		/* counter Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ATMEL_TC_RA	0x14		/* register A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ATMEL_TC_RB	0x18		/* register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ATMEL_TC_RC	0x1c		/* register C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ATMEL_TC_SR	0x20		/* status (read-only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Status-only flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define     ATMEL_TC_CLKSTA	(1 << 16)	/* clock enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define     ATMEL_TC_MTIOA	(1 << 17)	/* TIOA mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define     ATMEL_TC_MTIOB	(1 << 18)	/* TIOB mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ATMEL_TC_IER	0x24		/* interrupt enable (write-only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ATMEL_TC_IDR	0x28		/* interrupt disable (write-only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ATMEL_TC_IMR	0x2c		/* interrupt mask (read-only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Status and IRQ flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define     ATMEL_TC_COVFS	(1 <<  0)	/* counter overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define     ATMEL_TC_LOVRS	(1 <<  1)	/* load overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define     ATMEL_TC_CPAS	(1 <<  2)	/* RA compare */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define     ATMEL_TC_CPBS	(1 <<  3)	/* RB compare */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define     ATMEL_TC_CPCS	(1 <<  4)	/* RC compare */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define     ATMEL_TC_LDRAS	(1 <<  5)	/* RA loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define     ATMEL_TC_LDRBS	(1 <<  6)	/* RB loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define     ATMEL_TC_ETRGS	(1 <<  7)	/* external trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define     ATMEL_TC_ALL_IRQ	(ATMEL_TC_COVFS	| ATMEL_TC_LOVRS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 				 ATMEL_TC_CPAS | ATMEL_TC_CPBS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 				 ATMEL_TC_CPCS | ATMEL_TC_LDRAS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 				 ATMEL_TC_LDRBS | ATMEL_TC_ETRGS) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 				 /* all IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #endif