Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Atmel SFR (Special Function Registers) register offsets and bit definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2016 Atmel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _LINUX_MFD_SYSCON_ATMEL_SFR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _LINUX_MFD_SYSCON_ATMEL_SFR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AT91_SFR_DDRCFG		0x04	/* DDR Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AT91_SFR_CCFG_EBICSA	0x04	/* EBI Chip Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* 0x08 ~ 0x0c: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AT91_SFR_OHCIICR	0x10	/* OHCI INT Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AT91_SFR_OHCIISR	0x14	/* OHCI INT Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AT91_SFR_UTMICKTRIM	0x30	/* UTMI Clock Trimming Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AT91_SFR_UTMISWAP	0x3c	/* UTMI DP/DM Pin Swapping Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AT91_SFR_LS		0x7c	/* Light Sleep Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AT91_SFR_I2SCLKSEL	0x90	/* I2SC Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AT91_SFR_WPMR		0xe4	/* Write Protection Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Field definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AT91_SFR_CCFG_EBI_CSA(cs, val)		((val) << (cs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AT91_SFR_CCFG_EBI_DBPUC			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AT91_SFR_CCFG_EBI_DBPDC			BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AT91_SFR_CCFG_EBI_DRIVE			BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AT91_SFR_CCFG_NFD0_ON_D16		BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AT91_SFR_CCFG_DDR_MP_EN			BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AT91_SFR_OHCIICR_RES(x)			BIT(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AT91_SFR_OHCIICR_ARIE			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AT91_SFR_OHCIICR_APPSTART		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AT91_SFR_OHCIICR_USB_SUSP(x)		BIT(8 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AT91_SFR_OHCIICR_UDPPUDIS		BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AT91_OHCIICR_USB_SUSPEND		GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AT91_SFR_OHCIISR_RIS(x)			BIT(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AT91_UTMICKTRIM_FREQ			GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AT91_SFR_UTMISWAP_PORT(x)		BIT(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AT91_SFR_LS_VALUE(x)			BIT(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN	BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AT91_SFR_WPMR_WPEN			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AT91_SFR_WPMR_WPKEY_MASK		GENMASK(31, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif /* _LINUX_MFD_SYSCON_ATMEL_SFR_H */