Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2007 Andrew Victor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2007 Atmel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * SDRAM Controllers (SDRAMC) - System peripherals registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Based on AT91SAM9261 datasheet revision D.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef AT91SAM9_SDRAMC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AT91SAM9_SDRAMC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* SDRAM Controller (SDRAMC) registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AT91_SDRAMC_MR		0x00	/* SDRAM Controller Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define		AT91_SDRAMC_MODE	(0xf << 0)		/* Command Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define			AT91_SDRAMC_MODE_NORMAL		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define			AT91_SDRAMC_MODE_NOP		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define			AT91_SDRAMC_MODE_PRECHARGE	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define			AT91_SDRAMC_MODE_LMR		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define			AT91_SDRAMC_MODE_REFRESH	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define			AT91_SDRAMC_MODE_EXT_LMR	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define			AT91_SDRAMC_MODE_DEEP		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AT91_SDRAMC_TR		0x04	/* SDRAM Controller Refresh Timer Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define		AT91_SDRAMC_COUNT	(0xfff << 0)		/* Refresh Timer Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AT91_SDRAMC_CR		0x08	/* SDRAM Controller Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define		AT91_SDRAMC_NC		(3 << 0)		/* Number of Column Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define			AT91_SDRAMC_NC_8	(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define			AT91_SDRAMC_NC_9	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define			AT91_SDRAMC_NC_10	(2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define			AT91_SDRAMC_NC_11	(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define		AT91_SDRAMC_NR		(3 << 2)		/* Number of Row Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define			AT91_SDRAMC_NR_11	(0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define			AT91_SDRAMC_NR_12	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define			AT91_SDRAMC_NR_13	(2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define		AT91_SDRAMC_NB		(1 << 4)		/* Number of Banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define			AT91_SDRAMC_NB_2	(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define			AT91_SDRAMC_NB_4	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define		AT91_SDRAMC_CAS		(3 << 5)		/* CAS Latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define			AT91_SDRAMC_CAS_1	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define			AT91_SDRAMC_CAS_2	(2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define			AT91_SDRAMC_CAS_3	(3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define		AT91_SDRAMC_DBW		(1 << 7)		/* Data Bus Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define			AT91_SDRAMC_DBW_32	(0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define			AT91_SDRAMC_DBW_16	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define		AT91_SDRAMC_TWR		(0xf <<  8)		/* Write Recovery Delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define		AT91_SDRAMC_TRC		(0xf << 12)		/* Row Cycle Delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define		AT91_SDRAMC_TRP		(0xf << 16)		/* Row Precharge Delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define		AT91_SDRAMC_TRCD	(0xf << 20)		/* Row to Column Delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AT91_SDRAMC_LPR		0x10	/* SDRAM Controller Low Power Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define			AT91_SDRAMC_LPCB_DISABLE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define			AT91_SDRAMC_LPCB_SELF_REFRESH		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define			AT91_SDRAMC_LPCB_POWER_DOWN		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define			AT91_SDRAMC_LPCB_DEEP_POWER_DOWN	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define		AT91_SDRAMC_PASR		(7 << 4)	/* Partial Array Self Refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define		AT91_SDRAMC_TCSR		(3 << 8)	/* Temperature Compensated Self Refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define		AT91_SDRAMC_DS			(3 << 10)	/* Drive Strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define		AT91_SDRAMC_TIMEOUT		(3 << 12)	/* Time to define when Low Power Mode is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define			AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES	(0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	(2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AT91_SDRAMC_IER		0x14	/* SDRAM Controller Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AT91_SDRAMC_IDR		0x18	/* SDRAM Controller Interrupt Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AT91_SDRAMC_IMR		0x1C	/* SDRAM Controller Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AT91_SDRAMC_ISR		0x20	/* SDRAM Controller Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define		AT91_SDRAMC_RES		(1 << 0)		/* Refresh Error Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AT91_SDRAMC_MDR		0x24	/* SDRAM Memory Device Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define		AT91_SDRAMC_MD		(3 << 0)		/* Memory Device Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define			AT91_SDRAMC_MD_SDRAM		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif