^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __SOC_ARC_MCIP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __SOC_ARC_MCIP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <soc/arc/aux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ARC_REG_MCIP_BCR 0x0d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ARC_REG_MCIP_IDU_BCR 0x0D5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ARC_REG_GFRC_BUILD 0x0D6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ARC_REG_MCIP_CMD 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ARC_REG_MCIP_WDATA 0x601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ARC_REG_MCIP_READBACK 0x602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct mcip_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned int pad:8, param:16, cmd:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int cmd:8, param:16, pad:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CMD_INTRPT_GENERATE_IRQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CMD_INTRPT_GENERATE_ACK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CMD_INTRPT_READ_STATUS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CMD_INTRPT_CHECK_SOURCE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Semaphore Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CMD_SEMA_CLAIM_AND_READ 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CMD_SEMA_RELEASE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CMD_DEBUG_SET_MASK 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CMD_DEBUG_READ_MASK 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CMD_DEBUG_SET_SELECT 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CMD_DEBUG_READ_SELECT 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CMD_GFRC_READ_LO 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CMD_GFRC_READ_HI 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CMD_GFRC_SET_CORE 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CMD_GFRC_READ_CORE 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CMD_IDU_ENABLE 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CMD_IDU_DISABLE 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CMD_IDU_SET_MODE 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CMD_IDU_READ_MODE 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CMD_IDU_SET_DEST 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CMD_IDU_ACK_CIRQ 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CMD_IDU_SET_MASK 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IDU_M_TRIG_LEVEL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IDU_M_TRIG_EDGE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IDU_M_DISTRI_RR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IDU_M_DISTRI_DEST 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct mcip_bcr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int pad4:6, pw_dom:1, pad3:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) idu:1, pad2:1, num_cores:6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pad:1, gfrc:1, dbg:1, pw:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) msg:1, sem:1, ipi:1, slv:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int ver:8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) slv:1, ipi:1, sem:1, msg:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pw:1, dbg:1, gfrc:1, pad:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) num_cores:6, pad2:1, idu:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pad3:1, pw_dom:1, pad4:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct mcip_idu_bcr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int pad:21, cirqnum:3, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int ver:8, cirqnum:3, pad:21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Build register for IDU contains not an actual number of supported common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * interrupts but an exponent of 2 which must be multiplied by 4 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * get a number of supported common interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * MCIP programming model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * (param could be irq, common_irq, core_id ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * - More involved commands setup MCIP_WDATA with cmd specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * before invoking the simple command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline void __mcip_cmd(unsigned int cmd, unsigned int param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct mcip_cmd buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) buf.pad = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) buf.cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) buf.param = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) WRITE_AUX(ARC_REG_MCIP_CMD, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Setup additional data for a cmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Callers need to lock to ensure atomicity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) write_aux_reg(ARC_REG_MCIP_WDATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __mcip_cmd(cmd, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Read MCIP register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static inline unsigned int __mcip_cmd_read(unsigned int cmd, unsigned int param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __mcip_cmd(cmd, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return read_aux_reg(ARC_REG_MCIP_READBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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