Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2016 HGST, a Western Digital Company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef _RDMA_RW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define _RDMA_RW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <rdma/ib_verbs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <rdma/rdma_cm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <rdma/mr_pool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct rdma_rw_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	/* number of RDMA READ/WRITE WRs (not counting MR WRs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	u32			nr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	/* tag for the union below: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	u8			type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		/* for mapping a single SGE: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			struct ib_sge		sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 			struct ib_rdma_wr	wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		} single;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		/* for mapping of multiple SGEs: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			struct ib_sge		*sges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 			struct ib_rdma_wr	*wrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		} map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		/* for registering multiple WRs: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		struct rdma_rw_reg_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			struct ib_sge		sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			struct ib_rdma_wr	wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			struct ib_reg_wr	reg_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			struct ib_send_wr	inv_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			struct ib_mr		*mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		} *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int rdma_rw_ctx_init(struct rdma_rw_ctx *ctx, struct ib_qp *qp, u8 port_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		struct scatterlist *sg, u32 sg_cnt, u32 sg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		u64 remote_addr, u32 rkey, enum dma_data_direction dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void rdma_rw_ctx_destroy(struct rdma_rw_ctx *ctx, struct ib_qp *qp, u8 port_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		struct scatterlist *sg, u32 sg_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		enum dma_data_direction dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int rdma_rw_ctx_signature_init(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		u8 port_num, struct scatterlist *sg, u32 sg_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		struct scatterlist *prot_sg, u32 prot_sg_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		struct ib_sig_attrs *sig_attrs, u64 remote_addr, u32 rkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		enum dma_data_direction dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void rdma_rw_ctx_destroy_signature(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		u8 port_num, struct scatterlist *sg, u32 sg_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		struct scatterlist *prot_sg, u32 prot_sg_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		enum dma_data_direction dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct ib_send_wr *rdma_rw_ctx_wrs(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		u8 port_num, struct ib_cqe *cqe, struct ib_send_wr *chain_wr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int rdma_rw_ctx_post(struct rdma_rw_ctx *ctx, struct ib_qp *qp, u8 port_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		struct ib_cqe *cqe, struct ib_send_wr *chain_wr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int rdma_rw_mr_factor(struct ib_device *device, u8 port_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		unsigned int maxpages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void rdma_rw_init_qp(struct ib_device *dev, struct ib_qp_init_attr *attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int rdma_rw_init_mrs(struct ib_qp *qp, struct ib_qp_init_attr *attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void rdma_rw_cleanup_mrs(struct ib_qp *qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif /* _RDMA_RW_H */