^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * cisreg.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * The initial developer of the original code is David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (C) 1999 David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef _LINUX_CISREG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _LINUX_CISREG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Offsets from ConfigBase for CIS registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CISREG_COR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CISREG_CCSR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CISREG_PRR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CISREG_SCR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CISREG_ESR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CISREG_IOBASE_0 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CISREG_IOBASE_1 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CISREG_IOBASE_2 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CISREG_IOBASE_3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CISREG_IOSIZE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Configuration Option Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define COR_CONFIG_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define COR_MFC_CONFIG_MASK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define COR_FUNC_ENA 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define COR_ADDR_DECODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define COR_IREQ_ENA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define COR_LEVEL_REQ 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define COR_SOFT_RESET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Card Configuration and Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CCSR_INTR_ACK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CCSR_INTR_PENDING 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CCSR_POWER_DOWN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CCSR_AUDIO_ENA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CCSR_IOIS8 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CCSR_SIGCHG_ENA 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CCSR_CHANGED 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Pin Replacement Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PRR_WP_STATUS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PRR_READY_STATUS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PRR_BVD2_STATUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PRR_BVD1_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PRR_WP_EVENT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PRR_READY_EVENT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PRR_BVD2_EVENT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PRR_BVD1_EVENT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Socket and Copy Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SCR_SOCKET_NUM 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SCR_COPY_NUM 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Extended Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ESR_REQ_ATTN_ENA 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ESR_REQ_ATTN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * CardBus Function Status Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CBFN_EVENT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CBFN_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CBFN_STATE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CBFN_FORCE 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * These apply to all the CardBus function registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CBFN_WP 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CBFN_READY 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CBFN_BVD2 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CBFN_BVD1 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CBFN_GWAKE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CBFN_INTR 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Extra bits in the Function Event Mask Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define FEMR_BAM_ENA 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define FEMR_PWM_ENA 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define FEMR_WKUP_MASK 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Indirect Addressing Registers for Zoomed Video: these are addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * in common memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CISREG_ICTRL0 0x02 /* control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CISREG_ICTRL1 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CISREG_IADDR0 0x04 /* address registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CISREG_IADDR1 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CISREG_IADDR2 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CISREG_IADDR3 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CISREG_IDATA0 0x08 /* data registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CISREG_IDATA1 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ICTRL0_COMMON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ICTRL0_AUTOINC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ICTRL0_BYTEGRAN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif /* _LINUX_CISREG_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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