^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) ST-Ericsson AB 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Daniel Martensson / daniel.martensson@stericsson.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Dmitry.Tarnyagin / dmitry.tarnyagin@stericsson.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef CAIF_HSI_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CAIF_HSI_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <net/caif/caif_layer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <net/caif/caif_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Maximum number of CAIF frames that can reside in the same HSI frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CFHSI_MAX_PKTS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Maximum number of bytes used for the frame that can be embedded in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * HSI descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CFHSI_MAX_EMB_FRM_SZ 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Decides if HSI buffers should be prefilled with 0xFF pattern for easier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * debugging. Both TX and RX buffers will be filled before the transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CFHSI_DBG_PREFILL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Structure describing a HSI packet descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #pragma pack(1) /* Byte alignment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct cfhsi_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u16 cffrm_len[CFHSI_MAX_PKTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 emb_frm[CFHSI_MAX_EMB_FRM_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #pragma pack() /* Default alignment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Size of the complete HSI packet descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CFHSI_DESC_SZ (sizeof(struct cfhsi_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Size of the complete HSI packet descriptor excluding the optional embedded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * CAIF frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CFHSI_DESC_SHORT_SZ (CFHSI_DESC_SZ - CFHSI_MAX_EMB_FRM_SZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Maximum bytes transferred in one transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CFHSI_MAX_CAIF_FRAME_SZ 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CFHSI_MAX_PAYLOAD_SZ (CFHSI_MAX_PKTS * CFHSI_MAX_CAIF_FRAME_SZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Size of the complete HSI TX buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CFHSI_BUF_SZ_TX (CFHSI_DESC_SZ + CFHSI_MAX_PAYLOAD_SZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Size of the complete HSI RX buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CFHSI_BUF_SZ_RX ((2 * CFHSI_DESC_SZ) + CFHSI_MAX_PAYLOAD_SZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Bitmasks for the HSI descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CFHSI_PIGGY_DESC (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CFHSI_TX_STATE_IDLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CFHSI_TX_STATE_XFER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CFHSI_RX_STATE_DESC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CFHSI_RX_STATE_PAYLOAD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Bitmasks for power management. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CFHSI_WAKE_UP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CFHSI_WAKE_UP_ACK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CFHSI_WAKE_DOWN_ACK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CFHSI_AWAKE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CFHSI_WAKELOCK_HELD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CFHSI_SHUTDOWN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CFHSI_FLUSH_FIFO 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifndef CFHSI_INACTIVITY_TOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CFHSI_INACTIVITY_TOUT (1 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif /* CFHSI_INACTIVITY_TOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #ifndef CFHSI_WAKE_TOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CFHSI_WAKE_TOUT (3 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif /* CFHSI_WAKE_TOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #ifndef CFHSI_MAX_RX_RETRIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CFHSI_MAX_RX_RETRIES (10 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Structure implemented by the CAIF HSI driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct cfhsi_cb_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void (*tx_done_cb) (struct cfhsi_cb_ops *drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void (*rx_done_cb) (struct cfhsi_cb_ops *drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void (*wake_up_cb) (struct cfhsi_cb_ops *drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void (*wake_down_cb) (struct cfhsi_cb_ops *drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Structure implemented by HSI device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct cfhsi_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int (*cfhsi_up) (struct cfhsi_ops *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int (*cfhsi_down) (struct cfhsi_ops *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int (*cfhsi_tx) (u8 *ptr, int len, struct cfhsi_ops *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int (*cfhsi_rx) (u8 *ptr, int len, struct cfhsi_ops *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int (*cfhsi_wake_up) (struct cfhsi_ops *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int (*cfhsi_wake_down) (struct cfhsi_ops *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int (*cfhsi_get_peer_wake) (struct cfhsi_ops *dev, bool *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int (*cfhsi_fifo_occupancy) (struct cfhsi_ops *dev, size_t *occupancy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int (*cfhsi_rx_cancel)(struct cfhsi_ops *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct cfhsi_cb_ops *cb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Structure holds status of received CAIF frames processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct cfhsi_rx_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int nfrms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int pld_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bool piggy_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Priority mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CFHSI_PRIO_CTL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) CFHSI_PRIO_VI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) CFHSI_PRIO_VO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) CFHSI_PRIO_BEBK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CFHSI_PRIO_LAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct cfhsi_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 inactivity_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 aggregation_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 head_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 tail_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 q_high_mark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 q_low_mark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Structure implemented by CAIF HSI drivers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct cfhsi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct caif_dev_common cfdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct sk_buff_head qhead[CFHSI_PRIO_LAST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct cfhsi_cb_ops cb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct cfhsi_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int tx_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct cfhsi_rx_state rx_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct cfhsi_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 *rx_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 *rx_flip_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int flow_off_sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct work_struct wake_up_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct work_struct wake_down_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct work_struct out_of_sync_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct workqueue_struct *wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) wait_queue_head_t wake_up_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) wait_queue_head_t wake_down_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) wait_queue_head_t flush_fifo_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct timer_list inactivity_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct timer_list rx_slowpath_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* TX aggregation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int aggregation_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct timer_list aggregation_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned long bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) extern struct platform_driver cfhsi_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * enum ifla_caif_hsi - CAIF HSI NetlinkRT parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @IFLA_CAIF_HSI_INACTIVITY_TOUT: Inactivity timeout before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * taking the HSI wakeline down, in milliseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * When using RT Netlink to create, destroy or configure a CAIF HSI interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * enum ifla_caif_hsi is used to specify the configuration attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) enum ifla_caif_hsi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) __IFLA_CAIF_HSI_UNSPEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __IFLA_CAIF_HSI_INACTIVITY_TOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) __IFLA_CAIF_HSI_AGGREGATION_TOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __IFLA_CAIF_HSI_HEAD_ALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __IFLA_CAIF_HSI_TAIL_ALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __IFLA_CAIF_HSI_QHIGH_WATERMARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) __IFLA_CAIF_HSI_QLOW_WATERMARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __IFLA_CAIF_HSI_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct cfhsi_ops *cfhsi_get_ops(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #endif /* CAIF_HSI_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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