^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2017 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _MISC_CXLLIB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _MISC_CXLLIB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * cxl driver exports a in-kernel 'library' API which can be called by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * other drivers to help interacting with an IBM XSL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * tells whether capi is supported on the PCIe slot where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * device is seated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * dev: device whose slot needs to be checked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * flags: 0 for the time being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) bool cxllib_slot_is_supported(struct pci_dev *dev, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Returns the configuration parameters to be used by the XSL or device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * dev: device, used to find PHB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * struct cxllib_xsl_config:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * capi BAR address, i.e. 0x2000000000000-0x2FFFFFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * capi BAR size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * data send control (XSL_DSNCTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * dummy read address (XSL_DRA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CXL_XSL_CONFIG_VERSION1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct cxllib_xsl_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 version; /* format version for register encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 log_bar_size;/* log size of the capi_window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u64 bar_addr; /* address of the start of capi window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u64 dsnctl; /* matches definition of XSL_DSNCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u64 dra; /* real address that can be used for dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Activate capi for the pci host bridge associated with the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Can be extended to deactivate once we know how to do it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Device must be ready to accept messages from the CAPP unit and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * respond accordingly (TLB invalidates, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * PHB is switched to capi mode through calls to skiboot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * CAPP snooping is activated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * dev: device whose PHB should switch mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * mode: mode to switch to i.e. CAPI or PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * flags: options related to the mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum cxllib_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) CXL_MODE_CXL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CXL_MODE_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CXL_MODE_NO_DMA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CXL_MODE_DMA_TVT0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CXL_MODE_DMA_TVT1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int cxllib_switch_phb_mode(struct pci_dev *dev, enum cxllib_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Set the device for capi DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Define its dma_ops and dma offset so that allocations will be using TVT#1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * dev: device to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * flags: options. CXL_MODE_DMA_TVT1 should be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int cxllib_set_device_dma(struct pci_dev *dev, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Get the Process Element structure for the given thread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * task: task_struct for the context of the translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * translation_mode: whether addresses should be translated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * attr: attributes to fill up the Process Element structure from CAIA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct cxllib_pe_attributes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u64 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 lpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CXL_TRANSLATED_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CXL_REAL_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int cxllib_get_PE_attributes(struct task_struct *task,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long translation_mode, struct cxllib_pe_attributes *attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Handle memory fault.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Fault in all the pages of the specified buffer for the permissions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * provided in ‘flags’
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Shouldn't be called from interrupt context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * mm: struct mm for the thread faulting the pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * addr: base address of the buffer to page in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * size: size of the buffer to page in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * flags: permission requested (DSISR_ISSTORE...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int cxllib_handle_fault(struct mm_struct *mm, u64 addr, u64 size, u64 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif /* _MISC_CXLLIB_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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