Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Renesas RPC-IF core driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2018~2019 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2019 Macronix International Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2019-2020 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __RENESAS_RPC_IF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __RENESAS_RPC_IF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) enum rpcif_data_dir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	RPCIF_NO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	RPCIF_DATA_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	RPCIF_DATA_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct	rpcif_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		u8 buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		u8 opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		bool ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	} cmd, ocmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		u8 nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		u8 buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		bool ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	} addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		u8 ncycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		u8 buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	} dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		u8 nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		u8 buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		bool ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	} option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		u8 buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		unsigned int nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		enum rpcif_data_dir dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		bool ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			void *in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			const void *out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		} buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	} data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct	rpcif {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	void __iomem *dirmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	enum rpcif_data_dir dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	u8 bus_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	void *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	u32 xferlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	u32 smcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	u32 smadr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	u32 command;		/* DRCMR or SMCMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	u32 option;		/* DROPR or SMOPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	u32 enable;		/* DRENR or SMENR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	u32 dummy;		/* DRDMCR or SMDMCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	u32 ddr;		/* DRDRENR or SMDRENR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int  rpcif_sw_init(struct rpcif *rpc, struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void rpcif_hw_init(struct rpcif *rpc, bool hyperflash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void rpcif_enable_rpm(struct rpcif *rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void rpcif_disable_rpm(struct rpcif *rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 		   size_t *len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int rpcif_manual_xfer(struct rpcif *rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif // __RENESAS_RPC_IF_H