^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * vsp1.h -- R-Car VSP1 API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __MEDIA_VSP1_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __MEDIA_VSP1_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) int vsp1_du_init(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define VSP1_DU_STATUS_COMPLETE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define VSP1_DU_STATUS_WRITEBACK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * struct vsp1_du_lif_config - VSP LIF configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @width: output frame width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @height: output frame height
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @interlaced: true for interlaced pipelines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @callback: frame completion callback function (optional). When a callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * is provided, the VSP driver guarantees that it will be called once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * and only once for each vsp1_du_atomic_flush() call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @callback_data: data to be passed to the frame completion callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct vsp1_du_lif_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) bool interlaced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void (*callback)(void *data, unsigned int status, u32 crc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void *callback_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const struct vsp1_du_lif_config *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * struct vsp1_du_atomic_config - VSP atomic configuration parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @pixelformat: plane pixel format (V4L2 4CC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @pitch: line pitch in bytes for the first plane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @mem: DMA memory address for each plane of the frame buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @src: source rectangle in the frame buffer (integer coordinates)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @dst: destination rectangle on the display (integer coordinates)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @alpha: alpha value (0: fully transparent, 255: fully opaque)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @zpos: Z position of the plane (from 0 to number of planes minus 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct vsp1_du_atomic_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 pixelformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dma_addr_t mem[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct v4l2_rect src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct v4l2_rect dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int alpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int zpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * enum vsp1_du_crc_source - Source used for CRC calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @VSP1_DU_CRC_NONE: CRC calculation disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @VSP1_DU_CRC_PLANE: Perform CRC calculation on an input plane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @VSP1_DU_CRC_OUTPUT: Perform CRC calculation on the composed output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) enum vsp1_du_crc_source {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) VSP1_DU_CRC_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) VSP1_DU_CRC_PLANE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) VSP1_DU_CRC_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * struct vsp1_du_crc_config - VSP CRC computation configuration parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @source: source for CRC calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @index: index of the CRC source plane (when source is set to plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct vsp1_du_crc_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum vsp1_du_crc_source source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * struct vsp1_du_writeback_config - VSP writeback configuration parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @pixelformat: plane pixel format (V4L2 4CC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @pitch: line pitch in bytes for the first plane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @mem: DMA memory address for each plane of the frame buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct vsp1_du_writeback_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 pixelformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dma_addr_t mem[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * struct vsp1_du_atomic_pipe_config - VSP atomic pipe configuration parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @crc: CRC computation configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @writeback: writeback configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct vsp1_du_atomic_pipe_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct vsp1_du_crc_config crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct vsp1_du_writeback_config writeback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int rpf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) const struct vsp1_du_atomic_config *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const struct vsp1_du_atomic_pipe_config *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int vsp1_du_map_sg(struct device *dev, struct sg_table *sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void vsp1_du_unmap_sg(struct device *dev, struct sg_table *sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif /* __MEDIA_VSP1_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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