Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Media Bus API header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef V4L2_MEDIABUS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define V4L2_MEDIABUS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * How to use the V4L2_MBUS_* flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Flags are defined for each of the possible states and values of a media
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * bus configuration parameter. One and only one bit of each group of flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * shall be set by the users of the v4l2_subdev_pad_ops.get_mbus_config and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * v4l2_subdev_pad_ops.set_mbus_config operations to ensure that no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * conflicting settings are specified when reporting and setting the media bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * configuration with the two operations respectively. For example, it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * invalid to set or clear both the V4L2_MBUS_HSYNC_ACTIVE_HIGH and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * V4L2_MBUS_HSYNC_ACTIVE_LOW flag at the same time. Instead either flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * V4L2_MBUS_HSYNC_ACTIVE_HIGH or flag V4L2_MBUS_HSYNC_ACTIVE_LOW shall be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * set. The same is true for the V4L2_MBUS_CSI2_1/2/3/4_LANE flags group: only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * one of these four bits shall be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * TODO: replace the existing V4L2_MBUS_* flags with structures of fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * to avoid conflicting settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * In example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *     #define V4L2_MBUS_HSYNC_ACTIVE_HIGH             BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *     #define V4L2_MBUS_HSYNC_ACTIVE_LOW              BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * will be replaced by a field whose value reports the intended active state of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * the signal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *     unsigned int v4l2_mbus_hsync_active : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* Parallel flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * The client runs in master or in slave mode. By "Master mode" an operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * mode is meant, when the client (e.g., a camera sensor) is producing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * horizontal and vertical synchronisation. In "Slave mode" the host is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * providing these signals to the slave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define V4L2_MBUS_MASTER			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define V4L2_MBUS_SLAVE				BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * Signal polarity flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * Note: in BT.656 mode HSYNC, FIELD, and VSYNC are unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * V4L2_MBUS_[HV]SYNC* flags should be also used for specifying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * configuration of hardware that uses [HV]REF signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define V4L2_MBUS_HSYNC_ACTIVE_HIGH		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define V4L2_MBUS_HSYNC_ACTIVE_LOW		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define V4L2_MBUS_VSYNC_ACTIVE_HIGH		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define V4L2_MBUS_VSYNC_ACTIVE_LOW		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define V4L2_MBUS_PCLK_SAMPLE_RISING		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define V4L2_MBUS_PCLK_SAMPLE_FALLING		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define V4L2_MBUS_DATA_ACTIVE_HIGH		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define V4L2_MBUS_DATA_ACTIVE_LOW		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /* FIELD = 0/1 - Field1 (odd)/Field2 (even) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define V4L2_MBUS_FIELD_EVEN_HIGH		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* FIELD = 1/0 - Field1 (odd)/Field2 (even) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define V4L2_MBUS_FIELD_EVEN_LOW		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* Active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define V4L2_MBUS_VIDEO_SOG_ACTIVE_LOW		BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define V4L2_MBUS_DATA_ENABLE_HIGH		BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define V4L2_MBUS_DATA_ENABLE_LOW		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* Serial flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* CSI-2 D-PHY number of data lanes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define V4L2_MBUS_CSI2_1_LANE			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define V4L2_MBUS_CSI2_2_LANE			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define V4L2_MBUS_CSI2_3_LANE			BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define V4L2_MBUS_CSI2_4_LANE			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* CSI-2 Virtual Channel identifiers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define V4L2_MBUS_CSI2_CHANNEL_0		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define V4L2_MBUS_CSI2_CHANNEL_1		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define V4L2_MBUS_CSI2_CHANNEL_2		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define V4L2_MBUS_CSI2_CHANNEL_3		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* Clock non-continuous mode support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define V4L2_MBUS_CSI2_CONTINUOUS_CLOCK		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define V4L2_MBUS_CSI2_LANES		(V4L2_MBUS_CSI2_1_LANE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 					 V4L2_MBUS_CSI2_2_LANE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 					 V4L2_MBUS_CSI2_3_LANE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 					 V4L2_MBUS_CSI2_4_LANE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define V4L2_MBUS_CSI2_CHANNELS		(V4L2_MBUS_CSI2_CHANNEL_0 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 					 V4L2_MBUS_CSI2_CHANNEL_1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 					 V4L2_MBUS_CSI2_CHANNEL_2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 					 V4L2_MBUS_CSI2_CHANNEL_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * enum v4l2_mbus_type - media bus type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * @V4L2_MBUS_UNKNOWN:	unknown bus type, no V4L2 mediabus configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * @V4L2_MBUS_PARALLEL:	parallel interface with hsync and vsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * @V4L2_MBUS_BT656:	parallel interface with embedded synchronisation, can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  *			also be used for BT.1120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * @V4L2_MBUS_CSI1:	MIPI CSI-1 serial interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * @V4L2_MBUS_CCP2:	CCP2 (Compact Camera Port 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * @V4L2_MBUS_CSI2_DPHY: MIPI CSI-2 serial interface, with D-PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * @V4L2_MBUS_CSI2_CPHY: MIPI CSI-2 serial interface, with C-PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * @V4L2_MBUS_INVALID:	invalid bus type (keep as last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum v4l2_mbus_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	V4L2_MBUS_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	V4L2_MBUS_PARALLEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	V4L2_MBUS_BT656,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	V4L2_MBUS_CSI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	V4L2_MBUS_CCP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	V4L2_MBUS_CSI2_DPHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	V4L2_MBUS_CSI2_CPHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	V4L2_MBUS_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * struct v4l2_mbus_config - media bus configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * @type:	in: interface type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * @flags:	in / out: configuration flags, depending on @type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct v4l2_mbus_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	enum v4l2_mbus_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * v4l2_fill_pix_format - Ancillary routine that fills a &struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *	v4l2_pix_format fields from a &struct v4l2_mbus_framefmt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * @pix_fmt:	pointer to &struct v4l2_pix_format to be filled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * @mbus_fmt:	pointer to &struct v4l2_mbus_framefmt to be used as model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) v4l2_fill_pix_format(struct v4l2_pix_format *pix_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		     const struct v4l2_mbus_framefmt *mbus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	pix_fmt->width = mbus_fmt->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	pix_fmt->height = mbus_fmt->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	pix_fmt->field = mbus_fmt->field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	pix_fmt->colorspace = mbus_fmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	pix_fmt->ycbcr_enc = mbus_fmt->ycbcr_enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	pix_fmt->quantization = mbus_fmt->quantization;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	pix_fmt->xfer_func = mbus_fmt->xfer_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * v4l2_fill_pix_format - Ancillary routine that fills a &struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  *	v4l2_mbus_framefmt from a &struct v4l2_pix_format and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  *	data format code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * @mbus_fmt:	pointer to &struct v4l2_mbus_framefmt to be filled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * @pix_fmt:	pointer to &struct v4l2_pix_format to be used as model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * @code:	data format code (from &enum v4l2_mbus_pixelcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static inline void v4l2_fill_mbus_format(struct v4l2_mbus_framefmt *mbus_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 					 const struct v4l2_pix_format *pix_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			   u32 code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	mbus_fmt->width = pix_fmt->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	mbus_fmt->height = pix_fmt->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	mbus_fmt->field = pix_fmt->field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	mbus_fmt->colorspace = pix_fmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	mbus_fmt->ycbcr_enc = pix_fmt->ycbcr_enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	mbus_fmt->quantization = pix_fmt->quantization;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	mbus_fmt->xfer_func = pix_fmt->xfer_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	mbus_fmt->code = code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * v4l2_fill_pix_format - Ancillary routine that fills a &struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  *	v4l2_pix_format_mplane fields from a media bus structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  * @pix_mp_fmt:	pointer to &struct v4l2_pix_format_mplane to be filled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  * @mbus_fmt:	pointer to &struct v4l2_mbus_framefmt to be used as model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) v4l2_fill_pix_format_mplane(struct v4l2_pix_format_mplane *pix_mp_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			    const struct v4l2_mbus_framefmt *mbus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	pix_mp_fmt->width = mbus_fmt->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	pix_mp_fmt->height = mbus_fmt->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	pix_mp_fmt->field = mbus_fmt->field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	pix_mp_fmt->colorspace = mbus_fmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	pix_mp_fmt->ycbcr_enc = mbus_fmt->ycbcr_enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	pix_mp_fmt->quantization = mbus_fmt->quantization;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	pix_mp_fmt->xfer_func = mbus_fmt->xfer_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * v4l2_fill_pix_format - Ancillary routine that fills a &struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  *	v4l2_mbus_framefmt from a &struct v4l2_pix_format_mplane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  * @mbus_fmt:	pointer to &struct v4l2_mbus_framefmt to be filled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  * @pix_mp_fmt:	pointer to &struct v4l2_pix_format_mplane to be used as model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) v4l2_fill_mbus_format_mplane(struct v4l2_mbus_framefmt *mbus_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			     const struct v4l2_pix_format_mplane *pix_mp_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	mbus_fmt->width = pix_mp_fmt->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	mbus_fmt->height = pix_mp_fmt->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	mbus_fmt->field = pix_mp_fmt->field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	mbus_fmt->colorspace = pix_mp_fmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	mbus_fmt->ycbcr_enc = pix_mp_fmt->ycbcr_enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	mbus_fmt->quantization = pix_mp_fmt->quantization;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	mbus_fmt->xfer_func = pix_mp_fmt->xfer_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif