^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * tc35874x - Toshiba HDMI to CSI-2 bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you may redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the Free Software Foundation; version 2 of the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * References (c = chapter, p = page):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * REF_03 - Toshiba, TC358749XBG (H2C+), Functional Specification, Rev 0.74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #ifndef _TC35874X_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define _TC35874X_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum tc35874x_ddc5v_delays {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DDC5V_DELAY_0_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DDC5V_DELAY_50_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DDC5V_DELAY_100_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DDC5V_DELAY_200_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) enum tc35874x_hdmi_detection_delay {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) HDMI_MODE_DELAY_0_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) HDMI_MODE_DELAY_25_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) HDMI_MODE_DELAY_50_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) HDMI_MODE_DELAY_100_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct tc35874x_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* System clock connected to REFCLK (pin H5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* DDC +5V debounce delay to avoid spurious interrupts when the cable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * is connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Sets DDC5V_MODE in register DDC_CTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Default: DDC5V_DELAY_0_MS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) enum tc35874x_ddc5v_delays ddc5v_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bool enable_hdcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * The FIFO size is 512x32, so Toshiba recommend to set the default FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * level to somewhere in the middle (e.g. 300), so it can cover speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * mismatches in input and output ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u16 fifo_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u16 pll_prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u16 pll_fbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* CSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Calculate CSI parameters with REF_02 for the highest resolution your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * CSI interface can handle. The driver will adjust the number of CSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * lanes in use according to the pixel clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * The values in brackets are calculated with REF_02 when the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * bps pr lane is 823.5 MHz, and can serve as a starting point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 lineinitcnt; /* (0x00001770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 lptxtimecnt; /* (0x00000005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 tclk_headercnt; /* (0x00001d04) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 tclk_trailcnt; /* (0x00000000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 ths_headercnt; /* (0x00000505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 twakeup; /* (0x00004650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 tclk_postcnt; /* (0x00000000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 ths_trailcnt; /* (0x00000004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 hstxvregcnt; /* (0x00000005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* DVI->HDMI detection delay to avoid unnecessary switching between DVI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * and HDMI mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Sets HDMI_DET_V in register HDMI_DET.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Default: HDMI_MODE_DELAY_0_MS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) enum tc35874x_hdmi_detection_delay hdmi_detection_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Reset PHY automatically when TMDS clock goes from DC to AC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Sets PHY_AUTO_RST2 in register PHY_CTL2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Default: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) bool hdmi_phy_auto_reset_tmds_detected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Reset PHY automatically when TMDS clock passes 21 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Sets PHY_AUTO_RST3 in register PHY_CTL2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Default: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) bool hdmi_phy_auto_reset_tmds_in_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Reset PHY automatically when TMDS clock is detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Sets PHY_AUTO_RST4 in register PHY_CTL2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Default: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bool hdmi_phy_auto_reset_tmds_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Reset HDMI PHY automatically when hsync period is out of range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Sets H_PI_RST in register HV_RST.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Default: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bool hdmi_phy_auto_reset_hsync_out_of_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Reset HDMI PHY automatically when vsync period is out of range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Sets V_PI_RST in register HV_RST.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Default: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bool hdmi_phy_auto_reset_vsync_out_of_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* custom controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Audio sample rate in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TC35874X_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC35874X_BASE + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Audio present status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TC35874X_CID_AUDIO_PRESENT (V4L2_CID_USER_TC35874X_BASE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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