^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * upd64031a - NEC Electronics Ghost Reduction input defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * 2006 by Hans Verkuil (hverkuil@xs4all.nl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _UPD64031A_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _UPD64031A_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Ghost reduction modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define UPD64031A_GR_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define UPD64031A_GR_OFF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define UPD64031A_GR_THROUGH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Direct 3D/YCS Connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define UPD64031A_3DYCS_DISABLE (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define UPD64031A_3DYCS_COMPOSITE (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define UPD64031A_3DYCS_SVIDEO (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Composite sync digital separation circuit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define UPD64031A_COMPOSITE_EXTERNAL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Vertical sync digital separation circuit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UPD64031A_VERTICAL_EXTERNAL (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif