Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Digitizer with Horizontal PLL registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2009 Texas Instruments Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * This code is partially based upon the TVP5150 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * written by Mauro Carvalho Chehab <mchehab@kernel.org>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * and the TVP7002 driver in the TI LSP 2.10.00.14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef _TVP7002_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define _TVP7002_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TVP7002_MODULE_NAME "tvp7002"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * struct tvp7002_config - Platform dependent data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  *@clk_polarity: Clock polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  *		0 - Data clocked out on rising edge of DATACLK signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  *		1 - Data clocked out on falling edge of DATACLK signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  *@hs_polarity:  HSYNC polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  *		0 - Active low HSYNC output, 1 - Active high HSYNC output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  *@vs_polarity: VSYNC Polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  *		0 - Active low VSYNC output, 1 - Active high VSYNC output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  *@fid_polarity: Active-high Field ID polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  *		0 - The field ID output is set to logic 1 for an odd field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  *		    (field 1) and set to logic 0 for an even field (field 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  *		1 - Operation with polarity inverted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  *@sog_polarity: Active high Sync on Green output polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  *		0 - Normal operation, 1 - Operation with polarity inverted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct tvp7002_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	bool clk_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	bool hs_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	bool vs_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	bool fid_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	bool sog_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif