Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * tda1997x - NXP HDMI receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright 2017 Tim Harvey <tharvey@gateworks.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef _TDA1997X_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _TDA1997X_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Platform Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct tda1997x_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	enum v4l2_mbus_type vidout_bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	u32 vidout_bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	u8 vidout_port_cfg[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	/* pin polarity (1=invert) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	bool vidout_inv_de;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	bool vidout_inv_hs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	bool vidout_inv_vs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	bool vidout_inv_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	/* clock delays (0=-8, 1=-7 ... 15=+7 pixels) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	u8 vidout_delay_hs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	u8 vidout_delay_vs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	u8 vidout_delay_de;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	u8 vidout_delay_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	/* sync selections (controls how sync pins are derived) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	u8 vidout_sel_hs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	u8 vidout_sel_vs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	u8 vidout_sel_de;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	/* Audio Port Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	int audout_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	u32 audout_mclk_fs;	/* clock multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	u32 audout_width;	/* 13 or 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	u32 audout_layout;	/* layout0=AP0 layout1=AP0,AP1,AP2,AP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	bool audout_layoutauto;	/* audio layout dictated by pkt header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	bool audout_invert_clk;	/* data valid on rising edge of BCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	bool audio_auto_mute;	/* enable hardware audio auto-mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif