^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tc358743 - Toshiba HDMI to CSI-2 bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * References (c = chapter, p = page):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef _TC358743_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define _TC358743_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enum tc358743_ddc5v_delays {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) DDC5V_DELAY_0_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) DDC5V_DELAY_50_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) DDC5V_DELAY_100_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) DDC5V_DELAY_200_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) enum tc358743_hdmi_detection_delay {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) HDMI_MODE_DELAY_0_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) HDMI_MODE_DELAY_25_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) HDMI_MODE_DELAY_50_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) HDMI_MODE_DELAY_100_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct tc358743_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* System clock connected to REFCLK (pin H5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* DDC +5V debounce delay to avoid spurious interrupts when the cable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * is connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Sets DDC5V_MODE in register DDC_CTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Default: DDC5V_DELAY_0_MS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) enum tc358743_ddc5v_delays ddc5v_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) bool enable_hdcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * The FIFO size is 512x32, so Toshiba recommend to set the default FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * level to somewhere in the middle (e.g. 300), so it can cover speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * mismatches in input and output ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u16 fifo_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u16 pll_prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u16 pll_fbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* CSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Calculate CSI parameters with REF_02 for the highest resolution your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * CSI interface can handle. The driver will adjust the number of CSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * lanes in use according to the pixel clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * The values in brackets are calculated with REF_02 when the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * bps pr lane is 823.5 MHz, and can serve as a starting point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 lineinitcnt; /* (0x00001770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 lptxtimecnt; /* (0x00000005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 tclk_headercnt; /* (0x00001d04) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 tclk_trailcnt; /* (0x00000000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 ths_headercnt; /* (0x00000505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 twakeup; /* (0x00004650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 tclk_postcnt; /* (0x00000000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 ths_trailcnt; /* (0x00000004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 hstxvregcnt; /* (0x00000005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* DVI->HDMI detection delay to avoid unnecessary switching between DVI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * and HDMI mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Sets HDMI_DET_V in register HDMI_DET.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Default: HDMI_MODE_DELAY_0_MS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) enum tc358743_hdmi_detection_delay hdmi_detection_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Reset PHY automatically when TMDS clock goes from DC to AC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Sets PHY_AUTO_RST2 in register PHY_CTL2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Default: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bool hdmi_phy_auto_reset_tmds_detected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Reset PHY automatically when TMDS clock passes 21 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Sets PHY_AUTO_RST3 in register PHY_CTL2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Default: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) bool hdmi_phy_auto_reset_tmds_in_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Reset PHY automatically when TMDS clock is detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Sets PHY_AUTO_RST4 in register PHY_CTL2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Default: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) bool hdmi_phy_auto_reset_tmds_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Reset HDMI PHY automatically when hsync period is out of range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Sets H_PI_RST in register HV_RST.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Default: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) bool hdmi_phy_auto_reset_hsync_out_of_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Reset HDMI PHY automatically when vsync period is out of range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Sets V_PI_RST in register HV_RST.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Default: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bool hdmi_phy_auto_reset_vsync_out_of_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* custom controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Audio sample rate in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TC358743_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC358743_BASE + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Audio present status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TC358743_CID_AUDIO_PRESENT (V4L2_CID_USER_TC358743_BASE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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