^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) saa7115.h - definition for saa7111/3/4/5 inputs and frequency flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _SAA7115_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _SAA7115_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* s_routing inputs, outputs, and config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* SAA7111/3/4/5 HW inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SAA7115_COMPOSITE0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SAA7115_COMPOSITE1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SAA7115_COMPOSITE2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SAA7115_COMPOSITE3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SAA7115_COMPOSITE4 4 /* not available for the saa7111/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SAA7115_COMPOSITE5 5 /* not available for the saa7111/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SAA7115_SVIDEO0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SAA7115_SVIDEO1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SAA7115_SVIDEO2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SAA7115_SVIDEO3 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SAA7115_IPORT_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SAA7115_IPORT_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* SAA7111 specific outputs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SAA7111_VBI_BYPASS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SAA7111_FMT_YUV422 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SAA7111_FMT_RGB 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SAA7111_FMT_CCIR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SAA7111_FMT_YUV411 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* config flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Register 0x85 should set bit 0 to 0 (it's 1 by default). This bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * controls the IDQ signal polarity which is set to 'inverted' if the bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * it 1 and to 'default' if it is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SAA7115_IDQ_IS_DEFAULT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* s_crystal_freq values and flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* SAA7115 v4l2_crystal_freq frequency values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SAA7115_FREQ_32_11_MHZ 32110000 /* 32.11 MHz crystal, SAA7114/5 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SAA7115_FREQ_24_576_MHZ 24576000 /* 24.576 MHz crystal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* SAA7115 v4l2_crystal_freq audio clock control flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3) /* SA 39, LRDIV, SAA7114/5 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* ===== SAA7113 Config enums ===== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Register 0x08 "Horizontal time constant" [Bit 3..4]:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Should be set to "Fast Locking Mode" according to the datasheet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * and that is the default setting in the gm7113c_init table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * saa7113_init sets this value to "VTR Mode". */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum saa7113_r08_htc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SAA7113_HTC_TV_MODE = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SAA7113_HTC_VTR_MODE, /* Default for saa7113_init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SAA7113_HTC_FAST_LOCKING_MODE = 0x03 /* Default for gm7113c_init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Register 0x10 "Output format selection" [Bit 6..7]:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Defaults to ITU_656 as specified in datasheet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) enum saa7113_r10_ofts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SAA7113_OFTS_ITU_656 = 0x0, /* Default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SAA7113_OFTS_VFLAG_BY_VREF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SAA7113_OFTS_VFLAG_BY_DATA_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Register 0x12 "Output control" [Bit 0..3 Or Bit 4..7]:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * This is used to select what data is output on the RTS0 and RTS1 pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * RTS1 [Bit 4..7] Defaults to DOT_IN. (This value can not be set for RTS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * RTS0 [Bit 0..3] Defaults to VIPB in gm7113c_init as specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * in the datasheet, but is set to HREF_HS in the saa7113_init table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum saa7113_r12_rts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SAA7113_RTS_DOT_IN = 0, /* OBS: Only for RTS1 (Default RTS1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SAA7113_RTS_VIPB, /* Default RTS0 For gm7113c_init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SAA7113_RTS_GPSW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SAA7115_RTS_HL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SAA7113_RTS_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SAA7113_RTS_DL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SAA7113_RTS_PLIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SAA7113_RTS_HREF_HS, /* Default RTS0 For saa7113_init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SAA7113_RTS_HS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) SAA7113_RTS_HQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SAA7113_RTS_ODD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SAA7113_RTS_VS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SAA7113_RTS_V123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SAA7113_RTS_VGATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SAA7113_RTS_VREF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) SAA7113_RTS_FID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * struct saa7115_platform_data - Allow overriding default initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @saa7113_force_gm7113c_init: Force the use of the gm7113c_init table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * instead of saa7113_init table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * (saa7113 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @saa7113_r08_htc: [R_08 - Bit 3..4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @saa7113_r10_vrln: [R_10 - Bit 3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * default: Disabled for gm7113c_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Enabled for saa7113c_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @saa7113_r10_ofts: [R_10 - Bit 6..7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @saa7113_r12_rts0: [R_12 - Bit 0..3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @saa7113_r12_rts1: [R_12 - Bit 4..7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @saa7113_r13_adlsb: [R_13 - Bit 7] - default: disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct saa7115_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) bool saa7113_force_gm7113c_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum saa7113_r08_htc *saa7113_r08_htc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) bool *saa7113_r10_vrln;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) enum saa7113_r10_ofts *saa7113_r10_ofts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) enum saa7113_r12_rts *saa7113_r12_rts0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enum saa7113_r12_rts *saa7113_r12_rts1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) bool *saa7113_r13_adlsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags