^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef MT9P031_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define MT9P031_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) struct v4l2_subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * struct mt9p031_platform_data - MT9P031 platform data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * @ext_freq: Input clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * @target_freq: Pixel clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct mt9p031_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) int ext_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) int target_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #endif