^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) cs53l32a.h - definition for cs53l32a inputs and outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _CS53L32A_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _CS53L32A_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* There are 2 physical inputs, but the second input can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) placed in two modes, the first mode bypasses the PGA (gain),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) the second goes through the PGA. Hence there are three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) possible inputs to choose from. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* CS53L32A HW inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CS53L32A_IN0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CS53L32A_IN1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CS53L32A_IN2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #endif