^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * adv7842 - Analog Devices ADV7842 video decoder driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _ADV7842_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _ADV7842_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Analog input muxing modes (AFE register 0x02, [2:0]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) enum adv7842_ain_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ADV7842_AIN1_2_3_NC_SYNC_1_2 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ADV7842_AIN4_5_6_NC_SYNC_2_1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ADV7842_AIN7_8_9_NC_SYNC_3_1 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ADV7842_AIN10_11_12_NC_SYNC_4_1 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ADV7842_AIN9_4_5_6_SYNC_2_1 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Bus rotation and reordering. This is used to specify component reordering on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * the board and describes the components order on the bus when the ADV7842
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * outputs RGB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum adv7842_bus_order {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ADV7842_BUS_ORDER_RGB, /* No operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ADV7842_BUS_ORDER_GRB, /* Swap 1-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ADV7842_BUS_ORDER_RBG, /* Swap 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ADV7842_BUS_ORDER_BGR, /* Swap 1-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ADV7842_BUS_ORDER_BRG, /* Rotate right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ADV7842_BUS_ORDER_GBR, /* Rotate left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Input Color Space (IO register 0x02, [7:4]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enum adv7842_inp_color_space {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ADV7842_INP_COLOR_SPACE_LIM_RGB = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ADV7842_INP_COLOR_SPACE_FULL_RGB = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ADV7842_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ADV7842_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ADV7842_INP_COLOR_SPACE_XVYCC_601 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ADV7842_INP_COLOR_SPACE_XVYCC_709 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ADV7842_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ADV7842_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ADV7842_INP_COLOR_SPACE_AUTO = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Select output format (IO register 0x03, [4:2]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) enum adv7842_op_format_mode_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ADV7842_OP_FORMAT_MODE0 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ADV7842_OP_FORMAT_MODE1 = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ADV7842_OP_FORMAT_MODE2 = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Mode of operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) enum adv7842_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ADV7842_MODE_SDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ADV7842_MODE_COMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ADV7842_MODE_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ADV7842_MODE_HDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Video standard select (IO register 0x00, [5:0]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum adv7842_vid_std_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* SDP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ADV7842_SDP_VID_STD_CVBS_SD_4x1 = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ADV7842_SDP_VID_STD_YC_SD4_x1 = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* HDMI GR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ADV7842_HDMI_GR_VID_STD_AUTO_GRAPH_MODE = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* HDMI COMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ADV7842_HDMI_COMP_VID_STD_HD_1250P = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) enum adv7842_select_input {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ADV7842_SELECT_HDMI_PORT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ADV7842_SELECT_HDMI_PORT_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ADV7842_SELECT_VGA_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ADV7842_SELECT_VGA_COMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ADV7842_SELECT_SDP_CVBS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ADV7842_SELECT_SDP_YC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum adv7842_drive_strength {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ADV7842_DR_STR_LOW = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ADV7842_DR_STR_MEDIUM_LOW = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ADV7842_DR_STR_MEDIUM_HIGH = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ADV7842_DR_STR_HIGH = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct adv7842_sdp_csc_coeff {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) bool manual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u16 scaling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u16 A1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u16 A2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u16 A3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u16 A4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u16 B1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u16 B2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 B3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u16 B4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 C1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u16 C2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 C3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u16 C4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct adv7842_sdp_io_sync_adjustment {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 hs_beg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 hs_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 de_beg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u16 de_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 vs_beg_o;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 vs_beg_e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 vs_end_o;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 vs_end_e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 de_v_beg_o;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 de_v_beg_e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 de_v_end_o;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 de_v_end_e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Platform dependent definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct adv7842_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* chip reset during probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned chip_reset:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned disable_pwrdnb:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned disable_cable_det_rst:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Analog input muxing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) enum adv7842_ain_sel ain_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Bus rotation and reordering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) enum adv7842_bus_order bus_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Select output format mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) enum adv7842_op_format_mode_sel op_format_mode_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Default mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) enum adv7842_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Default input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Video standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) enum adv7842_vid_std_select vid_std_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* IO register 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned alt_gamma:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* IO register 0x05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned blank_data:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned insert_av_codes:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned replicate_av_codes:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* IO register 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned output_bus_lsb_to_msb:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* IO register 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) enum adv7842_drive_strength dr_str_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) enum adv7842_drive_strength dr_str_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) enum adv7842_drive_strength dr_str_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * IO register 0x19: Adjustment to the LLC DLL phase in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * increments of 1/32 of a clock period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned llc_dll_phase:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* External RAM for 3-D comb or frame synchronizer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned sd_ram_size; /* ram size in MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned sd_ram_ddr:1; /* ddr or sdr sdram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* HDMI free run, CP-reg 0xBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned hdmi_free_run_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* 0 = Mode 0: run when there is no TMDS clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 1 = Mode 1: run when there is no TMDS clock or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) video resolution does not match programmed one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned hdmi_free_run_mode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* SDP free run, CP-reg 0xDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned sdp_free_run_auto:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned sdp_free_run_man_col_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned sdp_free_run_cbar_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned sdp_free_run_force:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* HPA manual (0) or auto (1), affects HDMI register 0x69 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned hpa_auto:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct adv7842_sdp_csc_coeff sdp_csc_coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct adv7842_sdp_io_sync_adjustment sdp_io_sync_625;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct adv7842_sdp_io_sync_adjustment sdp_io_sync_525;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* i2c addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 i2c_sdp_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 i2c_sdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 i2c_cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 i2c_vdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 i2c_afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 i2c_hdmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 i2c_repeater;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 i2c_edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 i2c_infoframe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 i2c_cec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 i2c_avlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* custom ioctl, used to test the external RAM that's used by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * deinterlacer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ADV7842_CMD_RAM_TEST _IO('V', BASE_VIDIOC_PRIVATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ADV7842_EDID_PORT_A 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ADV7842_EDID_PORT_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ADV7842_EDID_PORT_VGA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ADV7842_PAD_SOURCE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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