^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * adv7604 - Analog Devices ADV7604 video decoder driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _ADV7604_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _ADV7604_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Analog input muxing modes (AFE register 0x02, [2:0]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum adv7604_ain_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ADV7604_AIN9_4_5_6_SYNC_2_1 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Bus rotation and reordering. This is used to specify component reordering on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * the board and describes the components order on the bus when the ADV7604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * outputs RGB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) enum adv7604_bus_order {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ADV7604_BUS_ORDER_RGB, /* No operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ADV7604_BUS_ORDER_GRB, /* Swap 1-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ADV7604_BUS_ORDER_RBG, /* Swap 2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ADV7604_BUS_ORDER_BGR, /* Swap 1-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ADV7604_BUS_ORDER_BRG, /* Rotate right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ADV7604_BUS_ORDER_GBR, /* Rotate left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Input Color Space (IO register 0x02, [7:4]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum adv76xx_inp_color_space {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ADV76XX_INP_COLOR_SPACE_LIM_RGB = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ADV76XX_INP_COLOR_SPACE_FULL_RGB = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ADV76XX_INP_COLOR_SPACE_XVYCC_601 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ADV76XX_INP_COLOR_SPACE_XVYCC_709 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ADV76XX_INP_COLOR_SPACE_AUTO = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Select output format (IO register 0x03, [4:2]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) enum adv7604_op_format_mode_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ADV7604_OP_FORMAT_MODE0 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ADV7604_OP_FORMAT_MODE1 = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ADV7604_OP_FORMAT_MODE2 = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum adv76xx_drive_strength {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ADV76XX_DR_STR_MEDIUM_LOW = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ADV76XX_DR_STR_MEDIUM_HIGH = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ADV76XX_DR_STR_HIGH = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* INT1 Configuration (IO register 0x40, [1:0]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum adv76xx_int1_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ADV76XX_INT1_CONFIG_OPEN_DRAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ADV76XX_INT1_CONFIG_ACTIVE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ADV76XX_INT1_CONFIG_ACTIVE_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ADV76XX_INT1_CONFIG_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum adv76xx_page {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ADV76XX_PAGE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ADV7604_PAGE_AVLINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ADV76XX_PAGE_CEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ADV76XX_PAGE_INFOFRAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ADV7604_PAGE_ESDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ADV7604_PAGE_DPP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ADV76XX_PAGE_AFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ADV76XX_PAGE_REP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ADV76XX_PAGE_EDID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ADV76XX_PAGE_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ADV76XX_PAGE_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ADV76XX_PAGE_CP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ADV7604_PAGE_VDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ADV76XX_PAGE_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Platform dependent definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct adv76xx_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned disable_pwrdnb:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned disable_cable_det_rst:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int default_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Analog input muxing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) enum adv7604_ain_sel ain_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Bus rotation and reordering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) enum adv7604_bus_order bus_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Select output format mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) enum adv7604_op_format_mode_sel op_format_mode_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Configuration of the INT1 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) enum adv76xx_int1_config int1_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* IO register 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned alt_gamma:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* IO register 0x05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned blank_data:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned insert_av_codes:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned replicate_av_codes:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* IO register 0x06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned inv_vs_pol:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned inv_hs_pol:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned inv_llc_pol:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* IO register 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) enum adv76xx_drive_strength dr_str_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enum adv76xx_drive_strength dr_str_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum adv76xx_drive_strength dr_str_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* IO register 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned output_bus_lsb_to_msb:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Free run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned hdmi_free_run_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* i2c addresses: 0 == use default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 i2c_addresses[ADV76XX_PAGE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) enum adv76xx_pad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ADV76XX_PAD_HDMI_PORT_A = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ADV7604_PAD_HDMI_PORT_B = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ADV7604_PAD_HDMI_PORT_C = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ADV7604_PAD_HDMI_PORT_D = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ADV7604_PAD_VGA_RGB = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ADV7604_PAD_VGA_COMP = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* The source pad is either 1 (ADV7611) or 6 (ADV7604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ADV7604_PAD_SOURCE = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ADV7611_PAD_SOURCE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ADV76XX_PAD_MAX = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* notify events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ADV76XX_HOTPLUG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags