Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * These are the HEVC state controls for use with stateless HEVC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * codec drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * It turns out that these structs are not stable yet and will undergo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * more changes. So keep them private until they are stable and ready to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * become part of the official public API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef _HEVC_CTRLS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define _HEVC_CTRLS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /* The pixel format isn't stable at the moment and will likely be renamed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define V4L2_CID_MPEG_VIDEO_HEVC_SPS		(V4L2_CID_MPEG_BASE + 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define V4L2_CID_MPEG_VIDEO_HEVC_PPS		(V4L2_CID_MPEG_BASE + 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS	(V4L2_CID_MPEG_BASE + 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE	(V4L2_CID_MPEG_BASE + 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE	(V4L2_CID_MPEG_BASE + 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* enum v4l2_ctrl_type type values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define V4L2_CTRL_TYPE_HEVC_PPS 0x0121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) enum v4l2_mpeg_video_hevc_decode_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) enum v4l2_mpeg_video_hevc_start_code {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define V4L2_HEVC_SLICE_TYPE_B	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define V4L2_HEVC_SLICE_TYPE_P	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define V4L2_HEVC_SLICE_TYPE_I	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE		(1ULL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED			(1ULL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define V4L2_HEVC_SPS_FLAG_AMP_ENABLED				(1ULL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET		(1ULL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define V4L2_HEVC_SPS_FLAG_PCM_ENABLED				(1ULL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED		(1ULL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT		(1ULL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED		(1ULL << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED	(1ULL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* The controls are not stable at the moment and will likely be reworked. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) struct v4l2_ctrl_hevc_sps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	__u16	pic_width_in_luma_samples;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	__u16	pic_height_in_luma_samples;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	__u8	bit_depth_luma_minus8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	__u8	bit_depth_chroma_minus8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	__u8	log2_max_pic_order_cnt_lsb_minus4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	__u8	sps_max_dec_pic_buffering_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	__u8	sps_max_num_reorder_pics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	__u8	sps_max_latency_increase_plus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	__u8	log2_min_luma_coding_block_size_minus3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	__u8	log2_diff_max_min_luma_coding_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	__u8	log2_min_luma_transform_block_size_minus2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	__u8	log2_diff_max_min_luma_transform_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	__u8	max_transform_hierarchy_depth_inter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	__u8	max_transform_hierarchy_depth_intra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	__u8	pcm_sample_bit_depth_luma_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	__u8	pcm_sample_bit_depth_chroma_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	__u8	log2_min_pcm_luma_coding_block_size_minus3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	__u8	log2_diff_max_min_pcm_luma_coding_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	__u8	num_short_term_ref_pic_sets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	__u8	num_long_term_ref_pics_sps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	__u8	chroma_format_idc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	__u8	padding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	__u64	flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED	(1ULL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT			(1ULL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED		(1ULL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT			(1ULL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED		(1ULL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED		(1ULL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED			(1ULL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT	(1ULL << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED			(1ULL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED			(1ULL << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED		(1ULL << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define V4L2_HEVC_PPS_FLAG_TILES_ENABLED			(1ULL << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED		(1ULL << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED	(1ULL << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED	(1ULL << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER	(1ULL << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT		(1ULL << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT (1ULL << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct v4l2_ctrl_hevc_pps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	__u8	num_extra_slice_header_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	__s8	init_qp_minus26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	__u8	diff_cu_qp_delta_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	__s8	pps_cb_qp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	__s8	pps_cr_qp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	__u8	num_tile_columns_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	__u8	num_tile_rows_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	__u8	column_width_minus1[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	__u8	row_height_minus1[22];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	__s8	pps_beta_offset_div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	__s8	pps_tc_offset_div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	__u8	log2_parallel_merge_level_minus2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	__u8	padding[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	__u64	flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_BEFORE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_AFTER	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define V4L2_HEVC_DPB_ENTRIES_NUM_MAX		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_hevc_dpb_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	__u64	timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	__u8	rps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	__u8	field_pic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	__u16	pic_order_cnt[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	__u8	padding[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_hevc_pred_weight_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	__s8	delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	__s8	luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	__s8	delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	__s8	chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	__s8	delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	__s8	luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	__s8	delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	__s8	chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	__u8	padding[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	__u8	luma_log2_weight_denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	__s8	delta_chroma_log2_weight_denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA		(1ULL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA		(1ULL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED	(1ULL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO			(1ULL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT			(1ULL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0		(1ULL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV		(1ULL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED (1ULL << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT	(1ULL << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct v4l2_ctrl_hevc_slice_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	__u32	bit_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	__u32	data_bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	__u8	nal_unit_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	__u8	nuh_temporal_id_plus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	__u8	slice_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	__u8	colour_plane_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	__u16	slice_pic_order_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	__u8	num_ref_idx_l0_active_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	__u8	num_ref_idx_l1_active_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	__u8	collocated_ref_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	__u8	five_minus_max_num_merge_cand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	__s8	slice_qp_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	__s8	slice_cb_qp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	__s8	slice_cr_qp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	__s8	slice_act_y_qp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	__s8	slice_act_cb_qp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	__s8	slice_act_cr_qp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	__s8	slice_beta_offset_div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	__s8	slice_tc_offset_div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture timing SEI message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	__u8	pic_struct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	__u8	num_active_dpb_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	__u8	ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	__u8	ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	__u8	num_rps_poc_st_curr_before;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	__u8	num_rps_poc_st_curr_after;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	__u8	num_rps_poc_lt_curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	__u8	padding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct v4l2_hevc_pred_weight_table pred_weight_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	__u64	flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #endif