Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * These are the H.264 state controls for use with stateless H.264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * codec drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * It turns out that these structs are not stable yet and will undergo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * more changes. So keep them private until they are stable and ready to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * become part of the official public API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef _H264_CTRLS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define _H264_CTRLS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * Maximum DPB size, as specified by section 'A.3.1 Level limits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * common to the Baseline, Main, and Extended profiles'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define V4L2_H264_NUM_DPB_ENTRIES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define V4L2_H264_REF_LIST_LEN (2 * V4L2_H264_NUM_DPB_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* Our pixel format isn't stable at the moment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * This is put insanely high to avoid conflicting with controls that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * would be added during the phase where those controls are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * stable. It should be fixed eventually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define V4L2_CID_MPEG_VIDEO_H264_SPS		(V4L2_CID_MPEG_BASE+1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define V4L2_CID_MPEG_VIDEO_H264_PPS		(V4L2_CID_MPEG_BASE+1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX	(V4L2_CID_MPEG_BASE+1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS	(V4L2_CID_MPEG_BASE+1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS	(V4L2_CID_MPEG_BASE+1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE	(V4L2_CID_MPEG_BASE+1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define V4L2_CID_MPEG_VIDEO_H264_START_CODE	(V4L2_CID_MPEG_BASE+1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define V4L2_CID_MPEG_VIDEO_H264_PRED_WEIGHTS	(V4L2_CID_MPEG_BASE+1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) enum v4l2_mpeg_video_h264_decode_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	V4L2_MPEG_VIDEO_H264_DECODE_MODE_FRAME_BASED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) enum v4l2_mpeg_video_h264_start_code {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	V4L2_MPEG_VIDEO_H264_START_CODE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) struct v4l2_ctrl_h264_sps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	__u8 profile_idc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	__u8 constraint_set_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	__u8 level_idc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	__u8 seq_parameter_set_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	__u8 chroma_format_idc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	__u8 bit_depth_luma_minus8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	__u8 bit_depth_chroma_minus8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	__u8 log2_max_frame_num_minus4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	__u8 pic_order_cnt_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	__u8 log2_max_pic_order_cnt_lsb_minus4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	__u8 max_num_ref_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	__u8 num_ref_frames_in_pic_order_cnt_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	__s32 offset_for_ref_frame[255];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	__s32 offset_for_non_ref_pic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	__s32 offset_for_top_to_bottom_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	__u16 pic_width_in_mbs_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	__u16 pic_height_in_map_units_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	__u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE				0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define V4L2_H264_PPS_FLAG_WEIGHTED_PRED				0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE				0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT			0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) struct v4l2_ctrl_h264_pps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	__u8 pic_parameter_set_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	__u8 seq_parameter_set_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	__u8 num_slice_groups_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	__u8 num_ref_idx_l0_default_active_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	__u8 num_ref_idx_l1_default_active_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	__u8 weighted_bipred_idc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	__s8 pic_init_qp_minus26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	__s8 pic_init_qs_minus26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	__s8 chroma_qp_index_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	__s8 second_chroma_qp_index_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	__u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct v4l2_ctrl_h264_scaling_matrix {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	__u8 scaling_list_4x4[6][16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	__u8 scaling_list_8x8[6][64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct v4l2_h264_weight_factors {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	__s16 luma_weight[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	__s16 luma_offset[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	__s16 chroma_weight[32][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	__s16 chroma_offset[32][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define V4L2_H264_CTRL_PRED_WEIGHTS_REQUIRED(pps, slice) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	((((pps)->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 ((slice)->slice_type == V4L2_H264_SLICE_TYPE_P || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	  (slice)->slice_type == V4L2_H264_SLICE_TYPE_SP)) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 ((pps)->weighted_bipred_idc == 1 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	  (slice)->slice_type == V4L2_H264_SLICE_TYPE_B))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_ctrl_h264_pred_weights {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	__u16 luma_log2_weight_denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	__u16 chroma_log2_weight_denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct v4l2_h264_weight_factors weight_factors[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define V4L2_H264_SLICE_TYPE_P				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define V4L2_H264_SLICE_TYPE_B				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define V4L2_H264_SLICE_TYPE_I				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define V4L2_H264_SLICE_TYPE_SP				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define V4L2_H264_SLICE_TYPE_SI				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define V4L2_H264_TOP_FIELD_REF				0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define V4L2_H264_BOTTOM_FIELD_REF			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define V4L2_H264_FRAME_REF				0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct v4l2_h264_reference {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	__u8 fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* Index into v4l2_ctrl_h264_decode_params.dpb[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	__u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct v4l2_ctrl_h264_slice_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/* Offset in bits to slice_data() from the beginning of this slice. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	__u32 header_bit_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	__u32 first_mb_in_slice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	__u8 slice_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	__u8 colour_plane_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	__u8 redundant_pic_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	__u8 cabac_init_idc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	__s8 slice_qp_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	__s8 slice_qs_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	__u8 disable_deblocking_filter_idc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	__s8 slice_alpha_c0_offset_div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	__s8 slice_beta_offset_div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	__u8 num_ref_idx_l0_active_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	__u8 num_ref_idx_l1_active_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	__u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct v4l2_h264_reference ref_pic_list0[V4L2_H264_REF_LIST_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct v4l2_h264_reference ref_pic_list1[V4L2_H264_REF_LIST_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	__u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define V4L2_H264_DPB_ENTRY_FLAG_VALID		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define V4L2_H264_DPB_ENTRY_FLAG_FIELD		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct v4l2_h264_dpb_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	__u64 reference_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	__u32 pic_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	__u16 frame_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	__u8 fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	__u8 reserved[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* Note that field is indicated by v4l2_buffer.field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	__s32 top_field_order_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	__s32 bottom_field_order_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	__u32 flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct v4l2_ctrl_h264_decode_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	__u16 nal_ref_idc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	__u16 frame_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	__s32 top_field_order_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	__s32 bottom_field_order_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	__u16 idr_pic_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	__u16 pic_order_cnt_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	__s32 delta_pic_order_cnt_bottom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	__s32 delta_pic_order_cnt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	__s32 delta_pic_order_cnt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/* Size in bits of dec_ref_pic_marking() syntax element. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	__u32 dec_ref_pic_marking_bit_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/* Size in bits of pic order count syntax. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	__u32 pic_order_cnt_bit_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	__u32 slice_group_change_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	__u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	__u32 flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #endif