^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __SAA7146_VV__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __SAA7146_VV__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <media/v4l2-ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <media/v4l2-fh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <media/drv-intf/saa7146.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <media/videobuf-dma-sg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MAX_SAA7146_CAPTURE_BUFFERS 32 /* arbitrary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define BUFFER_TIMEOUT (HZ/2) /* 0.5 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define WRITE_RPS0(x) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) dev->d_rps0.cpu_addr[ count++ ] = cpu_to_le32(x); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define WRITE_RPS1(x) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) dev->d_rps1.cpu_addr[ count++ ] = cpu_to_le32(x); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct saa7146_video_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 base_odd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 base_even;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 prot_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 base_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 num_line_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FORMAT_BYTE_SWAP 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FORMAT_IS_PLANAR 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct saa7146_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 pixelformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct saa7146_standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) v4l2_std_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int v_offset; /* number of lines of vertical offset before processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int v_field; /* number of lines in a field for HPS to process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int h_offset; /* horizontal offset of processing window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int h_pixels; /* number of horizontal pixels to process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int v_max_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int h_max_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* buffer for one video/vbi frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct saa7146_buf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* common v4l buffer stuff -- must be first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct videobuf_buffer vb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* saa7146 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct v4l2_pix_format *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int (*activate)(struct saa7146_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct saa7146_buf *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct saa7146_buf *next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* page tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct saa7146_pgtable pt[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct saa7146_dmaqueue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct saa7146_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct saa7146_buf *curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct timer_list timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct saa7146_overlay {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct saa7146_fh *fh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct v4l2_window win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct v4l2_clip clips[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int nclips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* per open data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct saa7146_fh {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Must be the first field! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct v4l2_fh fh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct saa7146_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* video capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct videobuf_queue video_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* vbi capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct videobuf_queue vbi_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int resources; /* resource management for device open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define STATUS_OVERLAY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define STATUS_CAPTURE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct saa7146_vv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* vbi capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct saa7146_dmaqueue vbi_dmaq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct v4l2_vbi_format vbi_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct timer_list vbi_read_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct file *vbi_read_timeout_file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* vbi workaround interrupt queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) wait_queue_head_t vbi_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int vbi_fieldcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct saa7146_fh *vbi_streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int video_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct saa7146_fh *video_fh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* video overlay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct saa7146_overlay ov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct v4l2_framebuffer ov_fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct saa7146_format *ov_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct saa7146_fh *ov_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* video capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct saa7146_dmaqueue video_dmaq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct v4l2_pix_format video_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) enum v4l2_field last_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* common: fixme? shouldn't this be in saa7146_fh?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (this leads to a more complicated question: shall the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) store the different settings (for example S_INPUT) for every open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) and restore it appropriately, or should all settings be common for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) all opens? currently, we do the latter, like all other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) drivers do... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct saa7146_standard *standard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int vflip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int hflip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int current_hps_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int current_hps_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct saa7146_dma d_clipping; /* pointer to clipping memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int resources; /* resource management for device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SAA7146_USE_PORT_B_FOR_VBI 0x2 /* use input port b for vbi hardware bug workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct saa7146_ext_vv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* information about the video capabilities of the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int inputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int audios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* additionally supported transmission standards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct saa7146_standard *stds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int num_stds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int (*std_callback)(struct saa7146_dev*, struct saa7146_standard *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* the extension can override this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct v4l2_ioctl_ops vid_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct v4l2_ioctl_ops vbi_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* pointer to the saa7146 core ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const struct v4l2_ioctl_ops *core_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct v4l2_file_operations vbi_fops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct saa7146_use_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void (*init)(struct saa7146_dev *, struct saa7146_vv *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int(*open)(struct saa7146_dev *, struct file *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) void (*release)(struct saa7146_dev *, struct file *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void (*irq_done)(struct saa7146_dev *, unsigned long status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ssize_t (*read)(struct file *, char __user *, size_t, loff_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* from saa7146_fops.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int saa7146_register_device(struct video_device *vid, struct saa7146_dev *dev, char *name, int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int saa7146_unregister_device(struct video_device *vid, struct saa7146_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void saa7146_buffer_finish(struct saa7146_dev *dev, struct saa7146_dmaqueue *q, int state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void saa7146_buffer_next(struct saa7146_dev *dev, struct saa7146_dmaqueue *q,int vbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int saa7146_buffer_queue(struct saa7146_dev *dev, struct saa7146_dmaqueue *q, struct saa7146_buf *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void saa7146_buffer_timeout(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void saa7146_dma_free(struct saa7146_dev* dev,struct videobuf_queue *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct saa7146_buf *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int saa7146_vv_init(struct saa7146_dev* dev, struct saa7146_ext_vv *ext_vv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int saa7146_vv_release(struct saa7146_dev* dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* from saa7146_hlp.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int saa7146_enable_overlay(struct saa7146_fh *fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void saa7146_disable_overlay(struct saa7146_fh *fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) void saa7146_set_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void saa7146_write_out_dma(struct saa7146_dev* dev, int which, struct saa7146_video_dma* vdma) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void saa7146_set_hps_source_and_sync(struct saa7146_dev *saa, int source, int sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void saa7146_set_gpio(struct saa7146_dev *saa, u8 pin, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* from saa7146_video.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) extern const struct v4l2_ioctl_ops saa7146_video_ioctl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) extern const struct v4l2_ioctl_ops saa7146_vbi_ioctl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) extern const struct saa7146_use_ops saa7146_video_uops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int saa7146_start_preview(struct saa7146_fh *fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int saa7146_stop_preview(struct saa7146_fh *fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) long saa7146_video_do_ioctl(struct file *file, unsigned int cmd, void *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int saa7146_s_ctrl(struct v4l2_ctrl *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* from saa7146_vbi.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) extern const struct saa7146_use_ops saa7146_vbi_uops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* resource management functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int saa7146_res_get(struct saa7146_fh *fh, unsigned int bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) void saa7146_res_free(struct saa7146_fh *fh, unsigned int bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define RESOURCE_DMA1_HPS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define RESOURCE_DMA2_CLP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define RESOURCE_DMA3_BRS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* saa7146 source inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SAA7146_HPS_SOURCE_PORT_A 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SAA7146_HPS_SOURCE_PORT_B 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SAA7146_HPS_SOURCE_YPB_CPA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SAA7146_HPS_SOURCE_YPA_CPB 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* sync inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SAA7146_HPS_SYNC_PORT_A 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SAA7146_HPS_SYNC_PORT_B 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* some memory sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* max. 16 clipping rectangles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SAA7146_CLIPPING_MEM (16 * 4 * sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* some defines for the various clipping-modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SAA7146_CLIPPING_RECT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SAA7146_CLIPPING_RECT_INVERTED 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SAA7146_CLIPPING_MASK 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SAA7146_CLIPPING_MASK_INVERTED 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* output formats: each entry holds four information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define RGB08_COMPOSED 0x0217 /* composed is used in the sense of "not-planar" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* this means: planar?=0, yuv2rgb-conversation-mode=2, dither=yes(=1), format-mode = 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define RGB15_COMPOSED 0x0213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define RGB16_COMPOSED 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define RGB24_COMPOSED 0x0201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define RGB32_COMPOSED 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define Y8 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define YUV411_COMPOSED 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define YUV422_COMPOSED 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* this means: planar?=1, yuv2rgb-conversion-mode=0, dither=no(=0), format-mode = b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define YUV411_DECOMPOSED 0x100b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define YUV422_DECOMPOSED 0x1009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define YUV420_DECOMPOSED 0x100a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IS_PLANAR(x) (x & 0xf000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* misc defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SAA7146_NO_SWAP (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SAA7146_TWO_BYTE_SWAP (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SAA7146_FOUR_BYTE_SWAP (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags