^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) msp3400.h - definition for msp3400 inputs and outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _MSP3400_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _MSP3400_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* msp3400 routing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ===============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) The msp3400 has a complicated routing scheme with many possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) combinations. The details are all in the datasheets but I will try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) to give a short description here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ======
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) There are 1) tuner inputs, 2) I2S inputs, 3) SCART inputs. You will have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) to select which tuner input to use and which SCART input to use. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) selected tuner input, the selected SCART input and all I2S inputs go to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) the DSP (the tuner input first goes through the demodulator).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) The DSP handles things like volume, bass/treble, balance, and some chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) have support for surround sound. It has several outputs: MAIN, AUX, I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) and SCART1/2. Each output can select which DSP input to use. So the MAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) output can select the tuner input while at the same time the SCART1 output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) uses the I2S input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) =======
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Most DSP outputs are also the outputs of the msp3400. However, the SCART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) outputs of the msp3400 can select which input to use: either the SCART1 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SCART2 output from the DSP, or the msp3400 SCART inputs, thus completely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bypassing the DSP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Summary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) =======
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) So to specify a complete routing scheme for the msp3400 you will have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) specify in the 'input' arg of the s_routing function:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 1) which tuner input to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 2) which SCART input to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 3) which DSP input to use for each DSP output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) And in the 'output' arg of the s_routing function you specify:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 1) which SCART input to use for each SCART output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Depending on how the msp is wired to the other components you can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ignore or mute certain inputs or outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) Also, depending on the msp version only a subset of the inputs or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) outputs may be present. At the end of this header some tables are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) added containing a list of what is available for each msp version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Inputs to the DSP unit: two independent selections have to be made:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 1) the tuner (SIF) input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 2) the SCART input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Bits 0-2 are used for the SCART input select, bit 3 is used for the tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) input, bits 4-7 are reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* SCART input to DSP selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MSP_IN_SCART1 0 /* Pin SC1_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MSP_IN_SCART2 1 /* Pin SC2_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MSP_IN_SCART3 2 /* Pin SC3_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MSP_IN_SCART4 3 /* Pin SC4_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MSP_IN_MONO 6 /* Pin MONO_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MSP_IN_MUTE 7 /* Mute DSP input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MSP_SCART_TO_DSP(in) (in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Tuner input to demodulator and DSP selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MSP_IN_TUNER1 0 /* Analog Sound IF input pin ANA_IN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MSP_IN_TUNER2 1 /* Analog Sound IF input pin ANA_IN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MSP_TUNER_TO_DSP(in) ((in) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* The msp has up to 5 DSP outputs, each output can independently select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) a DSP input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) The DSP outputs are: loudspeaker output (aka MAIN), headphones output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) (aka AUX), SCART1 DA output, SCART2 DA output and an I2S output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) There also is a quasi-peak detector output, but that is not used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) this driver and is set to the same input as the loudspeaker output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) Not all outputs are supported by all msp models. Setting the input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) of an unsupported output will be ignored by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) There are up to 16 DSP inputs to choose from, so each output is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) assigned 4 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) Note: the 44x8G can mix two inputs and feed the result back to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) DSP. This is currently not implemented. Also not implemented is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) multi-channel capable I2S3 input of the 44x0G. If someone can demonstrate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) a need for one of those features then additional support can be added. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MSP_DSP_IN_TUNER 0 /* Tuner DSP input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MSP_DSP_IN_SCART 2 /* SCART DSP input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MSP_DSP_IN_I2S1 5 /* I2S1 DSP input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MSP_DSP_IN_I2S2 6 /* I2S2 DSP input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MSP_DSP_IN_I2S3 7 /* I2S3 DSP input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MSP_DSP_IN_MAIN_AVC 11 /* MAIN AVC processed DSP input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MSP_DSP_IN_MAIN 12 /* MAIN DSP input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MSP_DSP_IN_AUX 13 /* AUX DSP input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MSP_DSP_TO_MAIN(in) ((in) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MSP_DSP_TO_AUX(in) ((in) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MSP_DSP_TO_SCART1(in) ((in) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MSP_DSP_TO_SCART2(in) ((in) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MSP_DSP_TO_I2S(in) ((in) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Output SCART select: the SCART outputs can select which input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) to use. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MSP_SC_IN_SCART1 0 /* SCART1 input, bypassing the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MSP_SC_IN_SCART2 1 /* SCART2 input, bypassing the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MSP_SC_IN_SCART3 2 /* SCART3 input, bypassing the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MSP_SC_IN_SCART4 3 /* SCART4 input, bypassing the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MSP_SC_IN_DSP_SCART1 4 /* DSP SCART1 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MSP_SC_IN_DSP_SCART2 5 /* DSP SCART2 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MSP_SC_IN_MONO 6 /* MONO input, bypassing the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MSP_SC_IN_MUTE 7 /* MUTE output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MSP_SC_TO_SCART1(in) (in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MSP_SC_TO_SCART2(in) ((in) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Shortcut macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MSP_INPUT(sc, t, main_aux_src, sc_i2s_src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) (MSP_SCART_TO_DSP(sc) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MSP_TUNER_TO_DSP(t) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MSP_DSP_TO_MAIN(main_aux_src) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MSP_DSP_TO_AUX(main_aux_src) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MSP_DSP_TO_SCART1(sc_i2s_src) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MSP_DSP_TO_SCART2(sc_i2s_src) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MSP_DSP_TO_I2S(sc_i2s_src))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MSP_INPUT_DEFAULT MSP_INPUT(MSP_IN_SCART1, MSP_IN_TUNER1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MSP_DSP_IN_TUNER, MSP_DSP_IN_TUNER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MSP_OUTPUT(sc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (MSP_SC_TO_SCART1(sc) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MSP_SC_TO_SCART2(sc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* This equals the RESET position of the msp3400 ACB register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MSP_OUTPUT_DEFAULT (MSP_SC_TO_SCART1(MSP_SC_IN_SCART3) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MSP_SC_TO_SCART2(MSP_SC_IN_DSP_SCART1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Tuner inputs vs. msp version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Chip TUNER_1 TUNER_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) -------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) msp34x0b y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) msp34x0c y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) msp34x0d y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) msp34x5d y n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) msp34x7d y n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) msp34x0g y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) msp34x1g y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) msp34x2g y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) msp34x5g y n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) msp34x7g y n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) msp44x0g y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) msp44x8g y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* SCART inputs vs. msp version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Chip SC1 SC2 SC3 SC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) -------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) msp34x0b y y y n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) msp34x0c y y y n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) msp34x0d y y y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) msp34x5d y y n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) msp34x7d y n n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) msp34x0g y y y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) msp34x1g y y y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) msp34x2g y y y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) msp34x5g y y n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) msp34x7g y n n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) msp44x0g y y y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) msp44x8g y y y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* DSP inputs vs. msp version (tuner and SCART inputs are always available) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Chip I2S1 I2S2 I2S3 MAIN_AVC MAIN AUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) msp34x0b y n n n n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) msp34x0c y y n n n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) msp34x0d y y n n n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) msp34x5d y y n n n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) msp34x7d n n n n n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) msp34x0g y y n n n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) msp34x1g y y n n n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) msp34x2g y y n y y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) msp34x5g y y n n n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) msp34x7g n n n n n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) msp44x0g y y y y y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) msp44x8g y y y n n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* DSP outputs vs. msp version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Chip MAIN AUX SCART1 SCART2 I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) msp34x0b y y y n y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) msp34x0c y y y n y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) msp34x0d y y y y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) msp34x5d y n y n y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) msp34x7d y n y n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) msp34x0g y y y y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) msp34x1g y y y y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) msp34x2g y y y y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) msp34x5g y n y n y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) msp34x7g y n y n n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) msp44x0g y y y y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) msp44x8g y y y y y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #endif /* MSP3400_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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