^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Samsung S5P/Exynos4 SoC series camera interface driver header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Sylwester Nawrocki <s.nawrocki@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef S5P_FIMC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define S5P_FIMC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <media/v4l2-dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Enumeration of data inputs to the camera subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) enum fimc_input {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) FIMC_INPUT_PARALLEL_0 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) FIMC_INPUT_PARALLEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) FIMC_INPUT_MIPI_CSI2_0 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) FIMC_INPUT_MIPI_CSI2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) FIMC_INPUT_WRITEBACK_A = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) FIMC_INPUT_WRITEBACK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) FIMC_INPUT_WRITEBACK_ISP = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Enumeration of the FIMC data bus types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum fimc_bus_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Camera parallel bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) FIMC_BUS_TYPE_ITU_601 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Camera parallel bus with embedded synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) FIMC_BUS_TYPE_ITU_656,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Camera MIPI-CSI2 serial bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) FIMC_BUS_TYPE_MIPI_CSI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* FIFO link from LCD controller (WriteBack A) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) FIMC_BUS_TYPE_LCD_WRITEBACK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* FIFO link from LCD controller (WriteBack B) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) FIMC_BUS_TYPE_LCD_WRITEBACK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* FIFO link from FIMC-IS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) FIMC_BUS_TYPE_ISP_WRITEBACK = FIMC_BUS_TYPE_LCD_WRITEBACK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define fimc_input_is_parallel(x) ((x) == 1 || (x) == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define fimc_input_is_mipi_csi(x) ((x) == 3 || (x) == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * The subdevices' group IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GRP_ID_SENSOR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GRP_ID_FIMC_IS_SENSOR (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GRP_ID_WRITEBACK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GRP_ID_CSIS (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GRP_ID_FIMC (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GRP_ID_FLITE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GRP_ID_FIMC_IS (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * struct fimc_source_info - video source description required for the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * interface configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @fimc_bus_type: FIMC camera input type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @sensor_bus_type: image sensor bus type, MIPI, ITU-R BT.601 etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @flags: the parallel sensor bus flags defining signals polarity (V4L2_MBUS_*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @mux_id: FIMC camera interface multiplexer index (separate for MIPI and ITU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct fimc_source_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) enum fimc_bus_type fimc_bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) enum fimc_bus_type sensor_bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u16 mux_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * v4l2_device notification id. This is only for internal use in the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Sensor subdevs should issue S5P_FIMC_TX_END_NOTIFY notification in single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * frame capture mode when there is only one VSYNC pulse issued by the sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * at beginning of the frame transmission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define S5P_FIMC_TX_END_NOTIFY _IO('e', 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define FIMC_MAX_PLANES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * struct fimc_fmt - color format data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @mbus_code: media bus pixel code, -1 if not applicable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @fourcc: fourcc code for this format, 0 if not applicable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @color: the driver's private color format id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @memplanes: number of physically non-contiguous data planes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @colplanes: number of physically contiguous data planes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @colorspace: v4l2 colorspace (V4L2_COLORSPACE_*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @depth: per plane driver's private 'number of bits per pixel'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @mdataplanes: bitmask indicating meta data plane(s), (1 << plane_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @flags: flags indicating which operation mode format applies to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct fimc_fmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 mbus_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u16 memplanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 colplanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 depth[FIMC_MAX_PLANES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u16 mdataplanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define FMT_FLAGS_CAM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define FMT_FLAGS_M2M_IN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define FMT_FLAGS_M2M_OUT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define FMT_FLAGS_M2M (1 << 1 | 1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define FMT_HAS_ALPHA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define FMT_FLAGS_COMPRESSED (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define FMT_FLAGS_WRITEBACK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define FMT_FLAGS_RAW_BAYER (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define FMT_FLAGS_YUV (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct exynos_media_pipeline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Media pipeline operations to be called from within a video node, i.e. the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * last entity within the pipeline. Implemented by related media device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct exynos_media_pipeline_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int (*prepare)(struct exynos_media_pipeline *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct media_entity *me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int (*unprepare)(struct exynos_media_pipeline *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int (*open)(struct exynos_media_pipeline *p, struct media_entity *me,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bool resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int (*close)(struct exynos_media_pipeline *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int (*set_stream)(struct exynos_media_pipeline *p, bool state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct exynos_video_entity {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct video_device vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct exynos_media_pipeline *pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct exynos_media_pipeline {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct media_pipeline mp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct exynos_media_pipeline_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline struct exynos_video_entity *vdev_to_exynos_video_entity(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct video_device *vdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return container_of(vdev, struct exynos_video_entity, vdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define fimc_pipeline_call(ent, op, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ((!(ent) || !(ent)->pipe) ? -ENOENT : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) (((ent)->pipe->ops && (ent)->pipe->ops->op) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) (ent)->pipe->ops->op(((ent)->pipe), ##args) : -ENOIOCTLCMD)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif /* S5P_FIMC_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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