Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *   cx25840.h - definition for cx25840/1/2/3 inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *   Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef _CX25840_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define _CX25840_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Note that the cx25840 driver requires that the bridge driver calls the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * v4l2_subdev's load_fw operation in order to load the driver's firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * This will load the firmware on the first invocation (further ones are NOP).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Without this the audio standard detection will fail and you will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * only get mono.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Alternatively, you can call the reset operation (this can be done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * multiple times if needed, each invocation will fully reinitialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * the device).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * Since loading the firmware is often problematic when the driver is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * compiled into the kernel I recommend postponing calling this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * until the first open of the video device. Another reason for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * postponing it is that loading this firmware takes a long time (seconds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * due to the slow i2c bus speed. So it will speed up the boot process if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * you can avoid loading the fw as long as the video device isn't used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) enum cx25840_video_input {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	/* Composite video inputs In1-In8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	CX25840_COMPOSITE1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	CX25840_COMPOSITE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	CX25840_COMPOSITE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	CX25840_COMPOSITE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	CX25840_COMPOSITE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	CX25840_COMPOSITE6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	CX25840_COMPOSITE7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	CX25840_COMPOSITE8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	 * S-Video inputs consist of one luma input (In1-In8) ORed with one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	 * chroma input (In5-In8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	CX25840_SVIDEO_LUMA1 = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	CX25840_SVIDEO_LUMA2 = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	CX25840_SVIDEO_LUMA3 = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	CX25840_SVIDEO_LUMA4 = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	CX25840_SVIDEO_LUMA5 = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	CX25840_SVIDEO_LUMA6 = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	CX25840_SVIDEO_LUMA7 = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	CX25840_SVIDEO_LUMA8 = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	CX25840_SVIDEO_CHROMA4 = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	CX25840_SVIDEO_CHROMA5 = 0x500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	CX25840_SVIDEO_CHROMA6 = 0x600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	CX25840_SVIDEO_CHROMA7 = 0x700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	CX25840_SVIDEO_CHROMA8 = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/* S-Video aliases for common luma/chroma combinations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	CX25840_SVIDEO1 = 0x510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	CX25840_SVIDEO2 = 0x620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	CX25840_SVIDEO3 = 0x730,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	CX25840_SVIDEO4 = 0x840,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/* Allow frames to specify specific input configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	CX25840_VIN1_CH1  = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	CX25840_VIN2_CH1  = 0x80000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	CX25840_VIN3_CH1  = 0x80000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	CX25840_VIN4_CH1  = 0x80000003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	CX25840_VIN5_CH1  = 0x80000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	CX25840_VIN6_CH1  = 0x80000005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	CX25840_VIN7_CH1  = 0x80000006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	CX25840_VIN8_CH1  = 0x80000007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	CX25840_VIN4_CH2  = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	CX25840_VIN5_CH2  = 0x80000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	CX25840_VIN6_CH2  = 0x80000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	CX25840_NONE_CH2  = 0x80000030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	CX25840_VIN7_CH3  = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	CX25840_VIN8_CH3  = 0x80000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	CX25840_NONE0_CH3 = 0x80000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	CX25840_NONE1_CH3 = 0x800000c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	CX25840_SVIDEO_ON = 0x80000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	CX25840_COMPONENT_ON = 0x80000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	CX25840_DIF_ON = 0x80000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * The defines below are used to set the chip video output settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * in the generic mode that can be enabled by calling the subdevice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * init core op.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  * The requested settings can be passed to the init core op as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * @val parameter and to the s_routing video op as @config parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * For details please refer to the section 3.7 Video Output Formatting and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * to Video Out Control 1 to 4 registers in the section 5.6 Video Decoder Core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * of the chip datasheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CX25840_VCONFIG_FMT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CX25840_VCONFIG_FMT_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CX25840_VCONFIG_FMT_BT601 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CX25840_VCONFIG_FMT_BT656 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CX25840_VCONFIG_FMT_VIP11 GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CX25840_VCONFIG_FMT_VIP2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CX25840_VCONFIG_RES_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CX25840_VCONFIG_RES_MASK GENMASK(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CX25840_VCONFIG_RES_8BIT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CX25840_VCONFIG_RES_10BIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CX25840_VCONFIG_VBIRAW_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CX25840_VCONFIG_VBIRAW_MASK GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CX25840_VCONFIG_VBIRAW_DISABLED BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CX25840_VCONFIG_VBIRAW_ENABLED BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CX25840_VCONFIG_ANCDATA_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CX25840_VCONFIG_ANCDATA_MASK GENMASK(8, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CX25840_VCONFIG_ANCDATA_DISABLED BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CX25840_VCONFIG_ANCDATA_ENABLED BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CX25840_VCONFIG_TASKBIT_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CX25840_VCONFIG_TASKBIT_MASK GENMASK(10, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CX25840_VCONFIG_TASKBIT_ZERO BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CX25840_VCONFIG_TASKBIT_ONE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CX25840_VCONFIG_ACTIVE_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CX25840_VCONFIG_ACTIVE_MASK GENMASK(12, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CX25840_VCONFIG_ACTIVE_COMPOSITE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CX25840_VCONFIG_ACTIVE_HORIZONTAL BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CX25840_VCONFIG_VALID_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CX25840_VCONFIG_VALID_MASK GENMASK(14, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CX25840_VCONFIG_VALID_NORMAL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CX25840_VCONFIG_VALID_ANDACTIVE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CX25840_VCONFIG_HRESETW_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CX25840_VCONFIG_HRESETW_MASK GENMASK(16, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CX25840_VCONFIG_HRESETW_NORMAL BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CX25840_VCONFIG_HRESETW_PIXCLK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CX25840_VCONFIG_CLKGATE_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CX25840_VCONFIG_CLKGATE_MASK GENMASK(18, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CX25840_VCONFIG_CLKGATE_NONE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CX25840_VCONFIG_CLKGATE_VALID BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CX25840_VCONFIG_CLKGATE_VALIDACTIVE GENMASK(18, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CX25840_VCONFIG_DCMODE_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CX25840_VCONFIG_DCMODE_MASK GENMASK(20, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CX25840_VCONFIG_DCMODE_DWORDS BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CX25840_VCONFIG_DCMODE_BYTES BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CX25840_VCONFIG_IDID0S_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CX25840_VCONFIG_IDID0S_MASK GENMASK(22, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CX25840_VCONFIG_IDID0S_NORMAL BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CX25840_VCONFIG_IDID0S_LINECNT BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CX25840_VCONFIG_VIPCLAMP_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CX25840_VCONFIG_VIPCLAMP_MASK GENMASK(24, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CX25840_VCONFIG_VIPCLAMP_ENABLED BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CX25840_VCONFIG_VIPCLAMP_DISABLED BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) enum cx25840_audio_input {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* Audio inputs: serial or In4-In8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	CX25840_AUDIO_SERIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	CX25840_AUDIO4 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	CX25840_AUDIO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	CX25840_AUDIO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	CX25840_AUDIO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	CX25840_AUDIO8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) enum cx25840_io_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	CX25840_PIN_DVALID_PRGM0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	CX25840_PIN_FIELD_PRGM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	CX25840_PIN_HRESET_PRGM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	CX25840_PIN_VRESET_HCTL_PRGM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	CX25840_PIN_IRQ_N_PRGM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	CX25840_PIN_IR_TX_PRGM6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	CX25840_PIN_IR_RX_PRGM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	CX25840_PIN_GPIO0_PRGM8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	CX25840_PIN_GPIO1_PRGM9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	CX25840_PIN_SA_SDIN,		/* Alternate GP Input only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	CX25840_PIN_SA_SDOUT,		/* Alternate GP Input only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	CX25840_PIN_PLL_CLK_PRGM7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	CX25840_PIN_CHIP_SEL_VIPCLK,	/* Output only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) enum cx25840_io_pad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* Output pads, these must match the actual chip register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	CX25840_PAD_DEFAULT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	CX25840_PAD_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	CX25840_PAD_VACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	CX25840_PAD_CBFLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	CX25840_PAD_VID_DATA_EXT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	CX25840_PAD_VID_DATA_EXT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	CX25840_PAD_GPO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	CX25840_PAD_GPO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	CX25840_PAD_GPO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	CX25840_PAD_GPO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	CX25840_PAD_IRQ_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	CX25840_PAD_AC_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	CX25840_PAD_AC_SDOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	CX25840_PAD_PLL_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	CX25840_PAD_VRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	CX25840_PAD_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	/* Pads for PLL_CLK output only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	CX25840_PAD_XTI_X5_DLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	CX25840_PAD_AUX_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	CX25840_PAD_VID_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	CX25840_PAD_XTI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* Input Pads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	CX25840_PAD_GPI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	CX25840_PAD_GPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	CX25840_PAD_GPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	CX25840_PAD_GPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) enum cx25840_io_pin_strength {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	CX25840_PIN_DRIVE_MEDIUM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	CX25840_PIN_DRIVE_SLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	CX25840_PIN_DRIVE_FAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) enum cx23885_io_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	CX23885_PIN_IR_RX_GPIO19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	CX23885_PIN_IR_TX_GPIO20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	CX23885_PIN_I2S_SDAT_GPIO21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	CX23885_PIN_I2S_WCLK_GPIO22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	CX23885_PIN_I2S_BCLK_GPIO23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	CX23885_PIN_IRQ_N_GPIO16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) enum cx23885_io_pad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	CX23885_PAD_IR_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	CX23885_PAD_GPIO19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	CX23885_PAD_IR_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	CX23885_PAD_GPIO20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	CX23885_PAD_I2S_SDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	CX23885_PAD_GPIO21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	CX23885_PAD_I2S_WCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	CX23885_PAD_GPIO22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	CX23885_PAD_I2S_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	CX23885_PAD_GPIO23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	CX23885_PAD_IRQ_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	CX23885_PAD_GPIO16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  * pvr150_workaround activates a workaround for a hardware bug that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  * present in Hauppauge PVR-150 (and possibly PVR-500) cards that have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  * certain NTSC tuners (tveeprom tuner model numbers 85, 99 and 112). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  * audio autodetect fails on some channels for these models and the workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  * is to select the audio standard explicitly. Many thanks to Hauppauge for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  * providing this information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  * This platform data only needs to be supplied by the ivtv driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct cx25840_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	int pvr150_workaround;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #endif