^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2009 Texas Instruments Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * vpss - video processing subsystem module header file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Include this header file if a driver needs to configure vpss system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * module. It exports a set of library functions for video drivers to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * configure vpss system module functions such as clock enable/disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * vpss interrupt mux to arm, and other common vpss system module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef _VPSS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define _VPSS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* selector for ccdc input selection on DM355 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enum vpss_ccdc_source_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) VPSS_CCDCIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) VPSS_HSSIIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) VPSS_PGLPBK, /* for DM365 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) VPSS_CCDCPG /* for DM365 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct vpss_sync_pol {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int ccdpg_hdpol:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned int ccdpg_vdpol:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct vpss_pg_frame_size {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) short hlpfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) short pplen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Used for enable/disable VPSS Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enum vpss_clock_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* DM355/DM365 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) VPSS_CCDC_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) VPSS_IPIPE_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) VPSS_H3A_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) VPSS_CFALD_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * When using VPSS_VENC_CLOCK_SEL in vpss_enable_clock() api
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * following applies:-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * en = 0 selects ENC_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * en = 1 selects ENC_CLK/2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) VPSS_VENC_CLOCK_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) VPSS_VPBE_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* DM365 only clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) VPSS_IPIPEIF_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) VPSS_RSZ_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) VPSS_BL_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * When using VPSS_PCLK_INTERNAL in vpss_enable_clock() api
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * following applies:-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * en = 0 disable internal PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * en = 1 enables internal PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) VPSS_PCLK_INTERNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * When using VPSS_PSYNC_CLOCK_SEL in vpss_enable_clock() api
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * following applies:-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * en = 0 enables MMR clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * en = 1 enables VPSS clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) VPSS_PSYNC_CLOCK_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) VPSS_LDC_CLOCK_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) VPSS_OSD_CLOCK_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) VPSS_FDIF_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) VPSS_LDC_CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* select input to ccdc on dm355 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* enable/disable a vpss clock, 0 - success, -1 - failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* set sync polarity, only for DM365*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void dm365_vpss_set_sync_pol(struct vpss_sync_pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* set the PG_FRAME_SIZE register, only for DM365 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* wbl reset for dm644x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum vpss_wbl_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) VPSS_PCR_AEW_WBL_0 = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) VPSS_PCR_AF_WBL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) VPSS_PCR_RSZ4_WBL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) VPSS_PCR_RSZ3_WBL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) VPSS_PCR_RSZ2_WBL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) VPSS_PCR_RSZ1_WBL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) VPSS_PCR_PREV_WBL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) VPSS_PCR_CCDC_WBL_O,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* clear wbl overflow flag for DM6446 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* set sync polarity*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void vpss_set_sync_pol(struct vpss_sync_pol sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* set the PG_FRAME_SIZE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * vpss_check_and_clear_interrupt - check and clear interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @irq - common enumerator for IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Following return values used:-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * 0 - interrupt occurred and cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * 1 - interrupt not occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * 2 - interrupt status not available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int vpss_dma_complete_interrupt(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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