^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2006-2009 Texas Instruments Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef _DM644X_CCDC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define _DM644X_CCDC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <media/davinci/ccdc_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <media/davinci/vpfe_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* enum for No of pixel per line to be avg. in Black Clamping*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) enum ccdc_sample_length {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) CCDC_SAMPLE_1PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) CCDC_SAMPLE_2PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) CCDC_SAMPLE_4PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) CCDC_SAMPLE_8PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) CCDC_SAMPLE_16PIXELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* enum for No of lines in Black Clamping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum ccdc_sample_line {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) CCDC_SAMPLE_1LINES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) CCDC_SAMPLE_2LINES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) CCDC_SAMPLE_4LINES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) CCDC_SAMPLE_8LINES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) CCDC_SAMPLE_16LINES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* enum for Alaw gamma width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum ccdc_gamma_width {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) CCDC_GAMMA_BITS_15_6, /* use bits 15-6 for gamma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) CCDC_GAMMA_BITS_14_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) CCDC_GAMMA_BITS_13_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) CCDC_GAMMA_BITS_12_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) CCDC_GAMMA_BITS_11_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) CCDC_GAMMA_BITS_10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) CCDC_GAMMA_BITS_09_0 /* use bits 9-0 for gamma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* returns the highest bit used for the gamma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static inline u8 ccdc_gamma_width_max_bit(enum ccdc_gamma_width width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return 15 - width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum ccdc_data_size {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) CCDC_DATA_16BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CCDC_DATA_15BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) CCDC_DATA_14BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) CCDC_DATA_13BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) CCDC_DATA_12BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) CCDC_DATA_11BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) CCDC_DATA_10BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) CCDC_DATA_8BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* returns the highest bit used for this data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline u8 ccdc_data_size_max_bit(enum ccdc_data_size sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return sz == CCDC_DATA_8BITS ? 7 : 15 - sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* structure for ALaw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct ccdc_a_law {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Enable/disable A-Law */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned char enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Gamma Width Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum ccdc_gamma_width gamma_wd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* structure for Black Clamping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct ccdc_black_clamp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned char enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* only if bClampEnable is TRUE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) enum ccdc_sample_length sample_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* only if bClampEnable is TRUE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) enum ccdc_sample_line sample_ln;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* only if bClampEnable is TRUE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned short start_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* only if bClampEnable is TRUE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned short sgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* only if bClampEnable is FALSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned short dc_sub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* structure for Black Level Compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct ccdc_black_compensation {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Constant value to subtract from Red component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) char r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Constant value to subtract from Gr component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) char gr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Constant value to subtract from Blue component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) char b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Constant value to subtract from Gb component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) char gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Structure for CCDC configuration parameters for raw capture mode passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * by application
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct ccdc_config_params_raw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* data size value from 8 to 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) enum ccdc_data_size data_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Structure for Optional A-Law */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct ccdc_a_law alaw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Structure for Optical Black Clamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct ccdc_black_clamp blk_clamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Structure for Black Compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct ccdc_black_compensation blk_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Define to enable/disable video port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define FP_NUM_BYTES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Define for extra pixel/line and extra lines/frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define NUM_EXTRAPIXELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define NUM_EXTRALINES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* settings for commonly used video formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CCDC_WIN_PAL {0, 0, 720, 576}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* ntsc square pixel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CCDC_WIN_VGA {0, 0, (640 + NUM_EXTRAPIXELS), (480 + NUM_EXTRALINES)}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Structure for CCDC configuration parameters for raw capture mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct ccdc_params_raw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* pixel format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) enum ccdc_pixfmt pix_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* progressive or interlaced frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) enum ccdc_frmfmt frm_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* video window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct v4l2_rect win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* field id polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) enum vpfe_pin_pol fid_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* vertical sync polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) enum vpfe_pin_pol vd_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* horizontal sync polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) enum vpfe_pin_pol hd_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* interleaved or separated fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) enum ccdc_buftype buf_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * enable to store the image in inverse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * order in memory(bottom to top)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned char image_invert_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* configurable parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct ccdc_config_params_raw config_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct ccdc_params_ycbcr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* pixel format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) enum ccdc_pixfmt pix_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* progressive or interlaced frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) enum ccdc_frmfmt frm_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* video window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct v4l2_rect win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* field id polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) enum vpfe_pin_pol fid_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* vertical sync polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) enum vpfe_pin_pol vd_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* horizontal sync polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) enum vpfe_pin_pol hd_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* enable BT.656 embedded sync mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int bt656_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* cb:y:cr:y or y:cb:y:cr in memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) enum ccdc_pixorder pix_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* interleaved or separated fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) enum ccdc_buftype buf_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #endif /* _DM644X_CCDC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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