^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2005-2009 Texas Instruments Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef _DM355_CCDC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define _DM355_CCDC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <media/davinci/ccdc_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <media/davinci/vpfe_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* enum for No of pixel per line to be avg. in Black Clamping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) enum ccdc_sample_length {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) CCDC_SAMPLE_1PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) CCDC_SAMPLE_2PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) CCDC_SAMPLE_4PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) CCDC_SAMPLE_8PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) CCDC_SAMPLE_16PIXELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* enum for No of lines in Black Clamping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum ccdc_sample_line {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) CCDC_SAMPLE_1LINES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) CCDC_SAMPLE_2LINES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) CCDC_SAMPLE_4LINES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) CCDC_SAMPLE_8LINES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) CCDC_SAMPLE_16LINES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* enum for Alaw gamma width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum ccdc_gamma_width {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) CCDC_GAMMA_BITS_13_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) CCDC_GAMMA_BITS_12_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) CCDC_GAMMA_BITS_11_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) CCDC_GAMMA_BITS_10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) CCDC_GAMMA_BITS_09_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum ccdc_colpats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) CCDC_RED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) CCDC_GREEN_RED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CCDC_GREEN_BLUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) CCDC_BLUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct ccdc_col_pat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum ccdc_colpats olop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) enum ccdc_colpats olep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum ccdc_colpats elop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) enum ccdc_colpats elep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum ccdc_datasft {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) CCDC_DATA_NO_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) CCDC_DATA_SHIFT_1BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) CCDC_DATA_SHIFT_2BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) CCDC_DATA_SHIFT_3BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) CCDC_DATA_SHIFT_4BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) CCDC_DATA_SHIFT_5BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) CCDC_DATA_SHIFT_6BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum ccdc_data_size {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) CCDC_DATA_16BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) CCDC_DATA_15BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) CCDC_DATA_14BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CCDC_DATA_13BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) CCDC_DATA_12BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) CCDC_DATA_11BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) CCDC_DATA_10BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CCDC_DATA_8BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) enum ccdc_mfilt1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) CCDC_NO_MEDIAN_FILTER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) CCDC_AVERAGE_FILTER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) CCDC_MEDIAN_FILTER1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) enum ccdc_mfilt2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) CCDC_NO_MEDIAN_FILTER2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) CCDC_AVERAGE_FILTER2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) CCDC_MEDIAN_FILTER2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* structure for ALaw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct ccdc_a_law {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Enable/disable A-Law */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned char enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Gamma Width Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum ccdc_gamma_width gamma_wd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* structure for Black Clamping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct ccdc_black_clamp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* only if bClampEnable is TRUE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned char b_clamp_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* only if bClampEnable is TRUE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) enum ccdc_sample_length sample_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* only if bClampEnable is TRUE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) enum ccdc_sample_line sample_ln;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* only if bClampEnable is TRUE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned short start_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* only if bClampEnable is FALSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned short sgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned short dc_sub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* structure for Black Level Compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct ccdc_black_compensation {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Constant value to subtract from Red component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned char r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Constant value to subtract from Gr component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned char gr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Constant value to subtract from Blue component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned char b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Constant value to subtract from Gb component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned char gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct ccdc_float {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int integer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int decimal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CCDC_CSC_COEFF_TABLE_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* structure for color space converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct ccdc_csc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned char enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * S8Q5. Use 2 decimal precision, user values range from -3.00 to 3.99.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * example - to use 1.03, set integer part as 1, and decimal part as 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * to use -1.03, set integer part as -1 and decimal part as 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct ccdc_float coeff[CCDC_CSC_COEFF_TABLE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Structures for Vertical Defect Correction*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) enum ccdc_vdf_csl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CCDC_VDF_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CCDC_VDF_HORZ_INTERPOL_SAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CCDC_VDF_HORZ_INTERPOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) enum ccdc_vdf_cuda {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CCDC_VDF_WHOLE_LINE_CORRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CCDC_VDF_UPPER_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) enum ccdc_dfc_mwr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CCDC_DFC_MWR_WRITE_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CCDC_DFC_WRITE_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) enum ccdc_dfc_mrd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CCDC_DFC_READ_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CCDC_DFC_READ_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) enum ccdc_dfc_ma_rst {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CCDC_DFC_INCR_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CCDC_DFC_CLR_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) enum ccdc_dfc_mclr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) CCDC_DFC_CLEAR_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) CCDC_DFC_CLEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct ccdc_dft_corr_ctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) enum ccdc_vdf_csl vdfcsl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) enum ccdc_vdf_cuda vdfcuda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned int vdflsft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct ccdc_dft_corr_mem_ctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) enum ccdc_dfc_mwr dfcmwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) enum ccdc_dfc_mrd dfcmrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) enum ccdc_dfc_ma_rst dfcmarst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) enum ccdc_dfc_mclr dfcmclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CCDC_DFT_TABLE_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Main Structure for vertical defect correction. Vertical defect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * correction can correct up to 16 defects if defects less than 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * then pad the rest with 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct ccdc_vertical_dft {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned char ver_dft_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned char gen_dft_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int saturation_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct ccdc_dft_corr_ctl dft_corr_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct ccdc_dft_corr_mem_ctl dft_corr_mem_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int dft_corr_horz[CCDC_DFT_TABLE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int dft_corr_vert[CCDC_DFT_TABLE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int dft_corr_sub1[CCDC_DFT_TABLE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int dft_corr_sub2[CCDC_DFT_TABLE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int dft_corr_sub3[CCDC_DFT_TABLE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct ccdc_data_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned char horz_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned char vert_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Structure for CCDC configuration parameters for raw capture mode passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * by application
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct ccdc_config_params_raw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* data shift to be applied before storing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) enum ccdc_datasft datasft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* data size value from 8 to 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) enum ccdc_data_size data_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* median filter for sdram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) enum ccdc_mfilt1 mfilt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) enum ccdc_mfilt2 mfilt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* low pass filter enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned char lpf_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Threshold of median filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int med_filt_thres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * horz and vertical data offset. Applicable for defect correction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * and lsc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct ccdc_data_offset data_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Structure for Optional A-Law */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct ccdc_a_law alaw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Structure for Optical Black Clamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct ccdc_black_clamp blk_clamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Structure for Black Compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct ccdc_black_compensation blk_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* structure for vertical Defect Correction Module Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct ccdc_vertical_dft vertical_dft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* structure for color space converter Module Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct ccdc_csc csc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* color patters for bayer capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct ccdc_col_pat col_pat_field0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct ccdc_col_pat col_pat_field1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CCDC_WIN_PAL {0, 0, 720, 576}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CCDC_WIN_VGA {0, 0, 640, 480}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct ccdc_params_ycbcr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* pixel format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) enum ccdc_pixfmt pix_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* progressive or interlaced frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) enum ccdc_frmfmt frm_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* video window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct v4l2_rect win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* field id polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) enum vpfe_pin_pol fid_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* vertical sync polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) enum vpfe_pin_pol vd_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* horizontal sync polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) enum vpfe_pin_pol hd_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* enable BT.656 embedded sync mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int bt656_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* cb:y:cr:y or y:cb:y:cr in memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) enum ccdc_pixorder pix_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* interleaved or separated fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) enum ccdc_buftype buf_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Gain applied to Raw Bayer data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct ccdc_gain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned short r_ye;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned short gr_cy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned short gb_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned short b_mg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Structure for CCDC configuration parameters for raw capture mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct ccdc_params_raw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* pixel format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) enum ccdc_pixfmt pix_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* progressive or interlaced frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) enum ccdc_frmfmt frm_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* video window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct v4l2_rect win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* field id polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) enum vpfe_pin_pol fid_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* vertical sync polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) enum vpfe_pin_pol vd_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* horizontal sync polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) enum vpfe_pin_pol hd_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* interleaved or separated fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) enum ccdc_buftype buf_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Gain values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct ccdc_gain gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int ccdc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* horizontal flip enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned char horz_flip_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * enable to store the image in inverse order in memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * (bottom to top)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned char image_invert_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Configurable part of raw data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct ccdc_config_params_raw config_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #endif /* DM355_CCDC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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