Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __DT_POWER_DELIVERY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __DT_POWER_DELIVERY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /* Power delivery Power Data Object definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define PDO_TYPE_FIXED		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define PDO_TYPE_BATT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define PDO_TYPE_VAR		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define PDO_TYPE_APDO		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define PDO_TYPE_SHIFT		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define PDO_TYPE_MASK		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define PDO_TYPE(t)	((t) << PDO_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define PDO_VOLT_MASK		0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define PDO_CURR_MASK		0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PDO_PWR_MASK		0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PDO_FIXED_DUAL_ROLE	(1 << 29) /* Power role swap supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PDO_FIXED_SUSPEND	(1 << 28) /* USB Suspend supported (Source) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PDO_FIXED_HIGHER_CAP	(1 << 28) /* Requires more than vSafe5V (Sink) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PDO_FIXED_EXTPOWER	(1 << 27) /* Externally powered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PDO_FIXED_USB_COMM	(1 << 26) /* USB communications capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PDO_FIXED_DATA_SWAP	(1 << 25) /* Data role swap supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PDO_FIXED_VOLT_SHIFT	10	/* 50mV units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PDO_FIXED_CURR_SHIFT	0	/* 10mA units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PDO_FIXED_VOLT(mv)	((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PDO_FIXED_CURR(ma)	((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PDO_FIXED(mv, ma, flags)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	(PDO_TYPE(PDO_TYPE_FIXED) | (flags) |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	 PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define VSAFE5V 5000 /* mv units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PDO_BATT_MAX_VOLT_SHIFT	20	/* 50mV units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PDO_BATT_MIN_VOLT_SHIFT	10	/* 50mV units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PDO_BATT_MAX_PWR_SHIFT	0	/* 250mW units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PDO_BATT(min_mv, max_mv, max_mw)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	(PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	 PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PDO_VAR_MAX_VOLT_SHIFT	20	/* 50mV units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PDO_VAR_MIN_VOLT_SHIFT	10	/* 50mV units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PDO_VAR_MAX_CURR_SHIFT	0	/* 10mA units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PDO_VAR(min_mv, max_mv, max_ma)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	(PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define APDO_TYPE_PPS		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define PDO_APDO_TYPE_SHIFT	28	/* Only valid value currently is 0x0 - PPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define PDO_APDO_TYPE_MASK	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PDO_APDO_TYPE(t)	((t) << PDO_APDO_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PDO_PPS_APDO_MAX_VOLT_SHIFT	17	/* 100mV units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define PDO_PPS_APDO_MIN_VOLT_SHIFT	8	/* 100mV units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define PDO_PPS_APDO_MAX_CURR_SHIFT	0	/* 50mA units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define PDO_PPS_APDO_VOLT_MASK	0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PDO_PPS_APDO_CURR_MASK	0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define PDO_PPS_APDO_MIN_VOLT(mv)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PDO_PPS_APDO_MAX_VOLT(mv)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PDO_PPS_APDO_MAX_CURR(ma)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define PDO_PPS_APDO(min_mv, max_mv, max_ma)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	(PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 PDO_PPS_APDO_MAX_CURR(max_ma))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)   * Based on "Table 6-14 Fixed Supply PDO - Sink" of "USB Power Delivery Specification Revision 3.0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)   * Version 1.2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)   * Initial current capability of the new source when vSafe5V is applied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define FRS_DEFAULT_POWER      1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define FRS_5V_1P5A            2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define FRS_5V_3A              3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * SVDM Identity Header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * <31>     :: data capable as a USB host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * <30>     :: data capable as a USB device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * <29:27>  :: product type (UFP / Cable / VPD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * <26>     :: modal operation supported (1b == yes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * <25:23>  :: product type (DFP) (SVDM version 2.0+ only; set to zero in version 1.0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * <22:21>  :: connector type (SVDM version 2.0+ only; set to zero in version 1.0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * <20:16>  :: Reserved, Shall be set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  * <15:0>   :: USB-IF assigned VID for this cable vendor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* PD Rev2.0 definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IDH_PTYPE_UNDEF		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* SOP Product Type (UFP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IDH_PTYPE_NOT_UFP       0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IDH_PTYPE_HUB           1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IDH_PTYPE_PERIPH        2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IDH_PTYPE_PSD           3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IDH_PTYPE_AMA           5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* SOP' Product Type (Cable Plug / VPD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IDH_PTYPE_NOT_CABLE     0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IDH_PTYPE_PCABLE        3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IDH_PTYPE_ACABLE        4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IDH_PTYPE_VPD           6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* SOP Product Type (DFP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IDH_PTYPE_NOT_DFP       0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IDH_PTYPE_DFP_HUB       1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IDH_PTYPE_DFP_HOST      2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IDH_PTYPE_DFP_PB        3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define VDO_IDH(usbh, usbd, ufp_cable, is_modal, dfp, conn, vid)                \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	((usbh) << 31 | (usbd) << 30 | ((ufp_cable) & 0x7) << 27                \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 | (is_modal) << 26 | ((dfp) & 0x7) << 23 | ((conn) & 0x3) << 21        \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 | ((vid) & 0xffff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  * Cert Stat VDO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * -------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * <31:0>  : USB-IF assigned XID for this cable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define VDO_CERT(xid)		((xid) & 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * Product VDO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * <31:16> : USB Product ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * <15:0>  : USB bcdDevice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define VDO_PRODUCT(pid, bcd)   (((pid) & 0xffff) << 16 | ((bcd) & 0xffff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * UFP VDO (PD Revision 3.0+ only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * --------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * <31:29> :: UFP VDO version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * <28>    :: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * <27:24> :: Device capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  * <23:22> :: Connector type (10b == receptacle, 11b == captive plug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * <21:11> :: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * <10:8>  :: Vconn power (AMA only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  * <7>     :: Vconn required (AMA only, 0b == no, 1b == yes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * <6>     :: Vbus required (AMA only, 0b == yes, 1b == no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * <5:3>   :: Alternate modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * <2:0>   :: USB highest speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* UFP VDO Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define UFP_VDO_VER1_2		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Device Capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DEV_USB2_CAPABLE	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DEV_USB2_BILLBOARD	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DEV_USB3_CAPABLE	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DEV_USB4_CAPABLE	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Connector Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define UFP_RECEPTACLE		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define UFP_CAPTIVE		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Vconn Power (AMA only, set to AMA_VCONN_NOT_REQ if Vconn is not required) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AMA_VCONN_PWR_1W	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AMA_VCONN_PWR_1W5	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AMA_VCONN_PWR_2W	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AMA_VCONN_PWR_3W	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define AMA_VCONN_PWR_4W	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define AMA_VCONN_PWR_5W	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AMA_VCONN_PWR_6W	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Vconn Required (AMA only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AMA_VCONN_NOT_REQ	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AMA_VCONN_REQ		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Vbus Required (AMA only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AMA_VBUS_REQ		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AMA_VBUS_NOT_REQ	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Alternate Modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define UFP_ALTMODE_NOT_SUPP	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define UFP_ALTMODE_TBT3	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define UFP_ALTMODE_RECFG	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define UFP_ALTMODE_NO_RECFG	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* USB Highest Speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define UFP_USB2_ONLY		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define UFP_USB32_GEN1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define UFP_USB32_4_GEN2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define UFP_USB4_GEN3		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define VDO_UFP(ver, cap, conn, vcpwr, vcr, vbr, alt, spd)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	(((ver) & 0x7) << 29 | ((cap) & 0xf) << 24 | ((conn) & 0x3) << 22	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 | ((vcpwr) & 0x7) << 8 | (vcr) << 7 | (vbr) << 6 | ((alt) & 0x7) << 3	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 | ((spd) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  * DFP VDO (PD Revision 3.0+ only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  * --------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  * <31:29> :: DFP VDO version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * <28:27> :: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  * <26:24> :: Host capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  * <23:22> :: Connector type (10b == receptacle, 11b == captive plug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  * <21:5>  :: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  * <4:0>   :: Port number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DFP_VDO_VER1_1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define HOST_USB2_CAPABLE	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define HOST_USB3_CAPABLE	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define HOST_USB4_CAPABLE	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DFP_RECEPTACLE		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DFP_CAPTIVE		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define VDO_DFP(ver, cap, conn, pnum)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	(((ver) & 0x7) << 29 | ((cap) & 0x7) << 24 | ((conn) & 0x3) << 22	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 | ((pnum) & 0x1f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  * Cable VDO (for both Passive and Active Cable VDO in PD Rev2.0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  * <31:28> :: Cable HW version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * <27:24> :: Cable FW version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * <23:20> :: Reserved, Shall be set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  * <19:18> :: type-C to Type-A/B/C/Captive (00b == A, 01 == B, 10 == C, 11 == Captive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * <17>    :: Reserved, Shall be set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * <16:13> :: cable latency (0001 == <10ns(~1m length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  * <12:11> :: cable termination type (11b == both ends active VCONN req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  * <10>    :: SSTX1 Directionality support (0b == fixed, 1b == cfgable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  * <9>     :: SSTX2 Directionality support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  * <8>     :: SSRX1 Directionality support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  * <7>     :: SSRX2 Directionality support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  * <6:5>   :: Vbus current handling capability (01b == 3A, 10b == 5A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  * <4>     :: Vbus through cable (0b == no, 1b == yes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  * <3>     :: SOP" controller present? (0b == no, 1b == yes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  * <2:0>   :: USB SS Signaling support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  * Passive Cable VDO (PD Rev3.0+)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  * ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  * <31:28> :: Cable HW version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  * <27:24> :: Cable FW version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  * <23:21> :: VDO version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  * <20>    :: Reserved, Shall be set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  * <19:18> :: Type-C to Type-C/Captive (10b == C, 11b == Captive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  * <17>    :: Reserved, Shall be set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  * <16:13> :: cable latency (0001 == <10ns(~1m length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  * <12:11> :: cable termination type (10b == Vconn not req, 01b == Vconn req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  * <10:9>  :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  * <8:7>   :: Reserved, Shall be set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  * <6:5>   :: Vbus current handling capability (01b == 3A, 10b == 5A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  * <4:3>   :: Reserved, Shall be set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  * <2:0>   :: USB highest speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  * Active Cable VDO 1 (PD Rev3.0+)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  * ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * <31:28> :: Cable HW version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * <27:24> :: Cable FW version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * <23:21> :: VDO version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * <20>    :: Reserved, Shall be set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  * <19:18> :: Connector type (10b == C, 11b == Captive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  * <17>    :: Reserved, Shall be set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  * <16:13> :: cable latency (0001 == <10ns(~1m length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  * <12:11> :: cable termination type (10b == one end active, 11b == both ends active VCONN req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  * <10:9>  :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  * <8>     :: SBU supported (0b == supported, 1b == not supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  * <7>     :: SBU type (0b == passive, 1b == active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  * <6:5>   :: Vbus current handling capability (01b == 3A, 10b == 5A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)  * <4>     :: Vbus through cable (0b == no, 1b == yes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  * <3>     :: SOP" controller present? (0b == no, 1b == yes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  * <2:0>   :: USB highest speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Cable VDO Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CABLE_VDO_VER1_0	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CABLE_VDO_VER1_3	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Connector Type (_ATYPE and _BTYPE are for PD Rev2.0 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CABLE_ATYPE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CABLE_BTYPE		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CABLE_CTYPE		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CABLE_CAPTIVE		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Cable Latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CABLE_LATENCY_1M	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CABLE_LATENCY_2M	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CABLE_LATENCY_3M	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CABLE_LATENCY_4M	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CABLE_LATENCY_5M	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CABLE_LATENCY_6M	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CABLE_LATENCY_7M	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define CABLE_LATENCY_7M_PLUS	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Cable Termination Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define PCABLE_VCONN_NOT_REQ	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define PCABLE_VCONN_REQ	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define ACABLE_ONE_END		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define ACABLE_BOTH_END		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Maximum Vbus Voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CABLE_MAX_VBUS_20V	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CABLE_MAX_VBUS_30V	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CABLE_MAX_VBUS_40V	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CABLE_MAX_VBUS_50V	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Active Cable SBU Supported/Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define ACABLE_SBU_SUPP		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define ACABLE_SBU_NOT_SUPP	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define ACABLE_SBU_PASSIVE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define ACABLE_SBU_ACTIVE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Vbus Current Handling Capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CABLE_CURR_DEF		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CABLE_CURR_3A		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CABLE_CURR_5A		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* USB SuperSpeed Signaling Support (PD Rev2.0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CABLE_USBSS_U2_ONLY	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CABLE_USBSS_U31_GEN1	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CABLE_USBSS_U31_GEN2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* USB Highest Speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CABLE_USB2_ONLY		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define CABLE_USB32_GEN1	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CABLE_USB32_4_GEN2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define CABLE_USB4_GEN3		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define VDO_CABLE(hw, fw, cbl, lat, term, tx1d, tx2d, rx1d, rx2d, cur, vps, sopp, usbss) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	(((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 | ((cbl) & 0x3) << 18		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	 | ((lat) & 0x7) << 13 | ((term) & 0x3) << 11 | (tx1d) << 10		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	 | (tx2d) << 9 | (rx1d) << 8 | (rx2d) << 7 | ((cur) & 0x3) << 5		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	 | (vps) << 4 | (sopp) << 3 | ((usbss) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define VDO_PCABLE(hw, fw, ver, conn, lat, term, vbm, cur, spd)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	(((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	 | ((conn) & 0x3) << 18 | ((lat) & 0xf) << 13 | ((term) & 0x3) << 11	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	 | ((vbm) & 0x3) << 9 | ((cur) & 0x3) << 5 | ((spd) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define VDO_ACABLE1(hw, fw, ver, conn, lat, term, vbm, sbu, sbut, cur, vbt, sopp, spd) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	(((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	 | ((conn) & 0x3) << 18	| ((lat) & 0xf) << 13 | ((term) & 0x3) << 11	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	 | ((vbm) & 0x3) << 9 | (sbu) << 8 | (sbut) << 7 | ((cur) & 0x3) << 5	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	 | (vbt) << 4 | (sopp) << 3 | ((spd) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)  * Active Cable VDO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)  * ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)  * <31:24> :: Maximum operating temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)  * <23:16> :: Shutdown temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)  * <15>    :: Reserved, Shall be set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)  * <14:12> :: U3/CLd power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)  * <11>    :: U3 to U0 transition mode (0b == direct, 1b == through U3S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)  * <10>    :: Physical connection (0b == copper, 1b == optical)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)  * <9>     :: Active element (0b == redriver, 1b == retimer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)  * <8>     :: USB4 supported (0b == yes, 1b == no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)  * <7:6>   :: USB2 hub hops consumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)  * <5>     :: USB2 supported (0b == yes, 1b == no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)  * <4>     :: USB3.2 supported (0b == yes, 1b == no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)  * <3>     :: USB lanes supported (0b == one lane, 1b == two lanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)  * <2>     :: Optically isolated active cable (0b == no, 1b == yes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)  * <1>     :: Reserved, Shall be set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)  * <0>     :: USB gen (0b == gen1, 1b == gen2+)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* U3/CLd Power*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define ACAB2_U3_CLD_10MW_PLUS	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define ACAB2_U3_CLD_10MW	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define ACAB2_U3_CLD_5MW	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define ACAB2_U3_CLD_1MW	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define ACAB2_U3_CLD_500UW	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define ACAB2_U3_CLD_200UW	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define ACAB2_U3_CLD_50UW	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Other Active Cable VDO 2 Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define ACAB2_U3U0_DIRECT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define ACAB2_U3U0_U3S		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define ACAB2_PHY_COPPER	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define ACAB2_PHY_OPTICAL	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define ACAB2_REDRIVER		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define ACAB2_RETIMER		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define ACAB2_USB4_SUPP		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define ACAB2_USB4_NOT_SUPP	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define ACAB2_USB2_SUPP		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define ACAB2_USB2_NOT_SUPP	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define ACAB2_USB32_SUPP	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define ACAB2_USB32_NOT_SUPP	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define ACAB2_LANES_ONE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define ACAB2_LANES_TWO		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define ACAB2_OPT_ISO_NO	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define ACAB2_OPT_ISO_YES	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define ACAB2_GEN_1		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define ACAB2_GEN_2_PLUS	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define VDO_ACABLE2(mtemp, stemp, u3p, trans, phy, ele, u4, hops, u2, u32, lane, iso, gen)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	(((mtemp) & 0xff) << 24 | ((stemp) & 0xff) << 16 | ((u3p) & 0x7) << 12	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	 | (trans) << 11 | (phy) << 10 | (ele) << 9 | (u4) << 8			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	 | ((hops) & 0x3) << 6 | (u2) << 5 | (u32) << 4 | (lane) << 3		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	 | (iso) << 2 | (gen))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)  * AMA VDO (PD Rev2.0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)  * ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)  * <31:28> :: Cable HW version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)  * <27:24> :: Cable FW version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)  * <23:12> :: Reserved, Shall be set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)  * <11>    :: SSTX1 Directionality support (0b == fixed, 1b == cfgable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)  * <10>    :: SSTX2 Directionality support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)  * <9>     :: SSRX1 Directionality support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)  * <8>     :: SSRX2 Directionality support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)  * <7:5>   :: Vconn power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)  * <4>     :: Vconn power required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)  * <3>     :: Vbus power required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)  * <2:0>   :: USB SS Signaling support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define VDO_AMA(hw, fw, tx1d, tx2d, rx1d, rx2d, vcpwr, vcr, vbr, usbss) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	(((hw) & 0x7) << 28 | ((fw) & 0x7) << 24			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	 | (tx1d) << 11 | (tx2d) << 10 | (rx1d) << 9 | (rx2d) << 8	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	 | ((vcpwr) & 0x7) << 5 | (vcr) << 4 | (vbr) << 3		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	 | ((usbss) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define PD_VDO_AMA_VCONN_REQ(vdo)	(((vdo) >> 4) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define PD_VDO_AMA_VBUS_REQ(vdo)	(((vdo) >> 3) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define AMA_USBSS_U2_ONLY	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define AMA_USBSS_U31_GEN1	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define AMA_USBSS_U31_GEN2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define AMA_USBSS_BBONLY	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)  * VPD VDO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)  * ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)  * <31:28> :: HW version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)  * <27:24> :: FW version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)  * <23:21> :: VDO version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)  * <20:17> :: Reserved, Shall be set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)  * <16:15> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)  * <14>    :: Charge through current support (0b == 3A, 1b == 5A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)  * <13>    :: Reserved, Shall be set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)  * <12:7>  :: Vbus impedance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)  * <6:1>   :: Ground impedance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)  * <0>     :: Charge through support (0b == no, 1b == yes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define VPD_VDO_VER1_0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define VPD_MAX_VBUS_20V	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define VPD_MAX_VBUS_30V	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define VPD_MAX_VBUS_40V	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define VPD_MAX_VBUS_50V	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define VPDCT_CURR_3A		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define VPDCT_CURR_5A		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define VPDCT_NOT_SUPP		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define VPDCT_SUPP		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define VDO_VPD(hw, fw, ver, vbm, curr, vbi, gi, ct)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	(((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	 | ((vbm) & 0x3) << 15 | (curr) << 14 | ((vbi) & 0x3f) << 7	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	 | ((gi) & 0x3f) << 1 | (ct))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #endif /* __DT_POWER_DELIVERY_H */