Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Header providing constants for Rockchip suspend bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2022, Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: XiaoDong.Huang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __DT_BINDINGS_RK3588_PM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __DT_BINDINGS_RK3588_PM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /******************************bits ops************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BIT(nr)				(1 << (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RKPM_SLP_ARMPD			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RKPM_SLP_ARMOFF			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RKPM_SLP_ARMOFF_DDRPD		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RKPM_SLP_ARMOFF_LOGOFF		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RKPM_SLP_ARMOFF_PMUOFF		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* all plls except ddr's pll*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RKPM_SLP_PMU_HW_PLLS_PD		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RKPM_SLP_PMU_PMUALIVE_32K	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RKPM_SLP_PMU_DIS_OSC		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RKPM_SLP_CLK_GT			BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RKPM_SLP_PMIC_LP		BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RKPM_SLP_32K_EXT		BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RKPM_SLP_TIME_OUT_WKUP		BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RKPM_SLP_PMU_DBG		BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* the wake up source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RKPM_CPU0_WKUP_EN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RKPM_CPU1_WKUP_EN		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RKPM_CPU2_WKUP_EN		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RKPM_CPU3_WKUP_EN		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RKPM_CPU4_WKUP_EN		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RKPM_CPU5_WKUP_EN		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RKPM_CPU6_WKUP_EN		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RKPM_CPU7_WKUP_EN		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RKPM_GPIO_WKUP_EN		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RKPM_SDMMC_WKUP_EN		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RKPM_SDIO_WKUP_EN		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RKPM_USB_WKUP_EN		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RKPM_UART0_WKUP_EN		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RKPM_VAD_WKUP_EN		BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RKPM_TIMER_WKUP_EN		BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RKPM_SYSINT_WKUP_EN		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RKPM_TIME_OUT_WKUP_EN		BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RKPM_PMUMCU_CEC_WKUP_EN		BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RKPM_PMUMCU_VAD_WKUP_EN		BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* io retention config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RKPM_EMMCIO_RET_EN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RKPM_VCCIO1_RET_EN		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RKPM_VCCIO2_RET_EN		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RKPM_VCCIO3_RET_EN		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RKPM_VCCIO4_RET_EN		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RKPM_VCCIO5_RET_EN		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RKPM_VCCIO6_RET_EN		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RKPM_PMUIO2_RET_EN		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif