Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _DT_BINDINGS_SAMSUNG_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _DT_BINDINGS_SAMSUNG_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define CLK_I2S_CDCLK		0 /* the CDCLK (CODECLKO) gate clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define CLK_I2S_RCLK_SRC	1 /* the RCLKSRC mux clock (corresponding to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 				   * RCLKSRC bit in IISMOD register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 				   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLK_I2S_RCLK_PSR	2 /* the RCLK prescaler divider clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 				   * (corresponding to the IISPSR register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 				   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #endif /* _DT_BINDINGS_SAMSUNG_I2S_H */