Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __DT_FSL_IMX_AUDMUX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __DT_FSL_IMX_AUDMUX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define MX27_AUDMUX_HPCR1_SSI0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define MX27_AUDMUX_HPCR2_SSI1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define MX27_AUDMUX_HPCR3_SSI_PINS_4	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define MX27_AUDMUX_PPCR1_SSI_PINS_1	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define MX27_AUDMUX_PPCR2_SSI_PINS_2	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MX27_AUDMUX_PPCR3_SSI_PINS_3	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MX31_AUDMUX_PORT1_SSI0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MX31_AUDMUX_PORT2_SSI1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MX31_AUDMUX_PORT3_SSI_PINS_3	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MX31_AUDMUX_PORT4_SSI_PINS_4	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MX31_AUDMUX_PORT5_SSI_PINS_5	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MX31_AUDMUX_PORT6_SSI_PINS_6	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MX31_AUDMUX_PORT7_SSI_PINS_7	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MX51_AUDMUX_PORT1_SSI0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MX51_AUDMUX_PORT2_SSI1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MX51_AUDMUX_PORT3		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MX51_AUDMUX_PORT4		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MX51_AUDMUX_PORT5		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MX51_AUDMUX_PORT6		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MX51_AUDMUX_PORT7		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * TFCSEL/RFCSEL (i.MX27) or TFSEL/TCSEL/RFSEL/RCSEL (i.MX31/51/53/6Q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * can be sourced from Rx/Tx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX_AUDMUX_RXFS			0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX_AUDMUX_RXCLK		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX_AUDMUX_V1_PCR_INMMASK(x)	((x) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX_AUDMUX_V1_PCR_INMEN		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX_AUDMUX_V1_PCR_TXRXEN	(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX_AUDMUX_V1_PCR_SYN		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX_AUDMUX_V1_PCR_RXDSEL(x)	(((x) & 0x7) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX_AUDMUX_V1_PCR_RFCSEL(x)	(((x) & 0xf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX_AUDMUX_V1_PCR_RCLKDIR	(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX_AUDMUX_V1_PCR_RFSDIR	(1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX_AUDMUX_V1_PCR_TFCSEL(x)	(((x) & 0xf) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX_AUDMUX_V1_PCR_TCLKDIR	(1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX_AUDMUX_V1_PCR_TFSDIR	(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX_AUDMUX_V2_PTCR_TFSDIR	(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX_AUDMUX_V2_PTCR_TFSEL(x)	(((x) & 0xf) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX_AUDMUX_V2_PTCR_TCLKDIR	(1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX_AUDMUX_V2_PTCR_TCSEL(x)	(((x) & 0xf) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX_AUDMUX_V2_PTCR_RFSDIR	(1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX_AUDMUX_V2_PTCR_RFSEL(x)	(((x) & 0xf) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX_AUDMUX_V2_PTCR_RCLKDIR	(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX_AUDMUX_V2_PTCR_RCSEL(x)	(((x) & 0xf) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX_AUDMUX_V2_PTCR_SYN		(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX_AUDMUX_V2_PDCR_RXDSEL(x)	(((x) & 0x7) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX_AUDMUX_V2_PDCR_TXRXEN	(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX_AUDMUX_V2_PDCR_MODE(x)	(((x) & 0x3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX_AUDMUX_V2_PDCR_INMMASK(x)	((x) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif /* __DT_FSL_IMX_AUDMUX_H */