Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * cs42l42.h -- CS42L42 ALSA SoC audio driver DT bindings header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright 2016 Cirrus Logic, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Author: James Schulman <james.schulman@cirrus.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Author: Brian Austin <brian.austin@cirrus.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Author: Michael White <michael.white@cirrus.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __DT_CS42L42_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __DT_CS42L42_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* HPOUT Load Capacity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CS42L42_HPOUT_LOAD_1NF		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CS42L42_HPOUT_LOAD_10NF		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* HPOUT Clamp to GND Override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CS42L42_HPOUT_CLAMP_EN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CS42L42_HPOUT_CLAMP_DIS		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Tip Sense Inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CS42L42_TS_INV_DIS			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CS42L42_TS_INV_EN			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Tip Sense Debounce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CS42L42_TS_DBNCE_0			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CS42L42_TS_DBNCE_125			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CS42L42_TS_DBNCE_250			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CS42L42_TS_DBNCE_500			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CS42L42_TS_DBNCE_750			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CS42L42_TS_DBNCE_1000			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CS42L42_TS_DBNCE_1250			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CS42L42_TS_DBNCE_1500			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Button Press Software Debounce Times */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CS42L42_BTN_DET_INIT_DBNCE_MIN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CS42L42_BTN_DET_INIT_DBNCE_DEFAULT	100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CS42L42_BTN_DET_INIT_DBNCE_MAX		200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CS42L42_BTN_DET_EVENT_DBNCE_MIN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CS42L42_BTN_DET_EVENT_DBNCE_MAX		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Button Detect Level Sensitivities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CS42L42_NUM_BIASES		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CS42L42_HS_DET_LEVEL_15		0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CS42L42_HS_DET_LEVEL_8		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CS42L42_HS_DET_LEVEL_4		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CS42L42_HS_DET_LEVEL_1		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CS42L42_HS_DET_LEVEL_MIN	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CS42L42_HS_DET_LEVEL_MAX	0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* HS Bias Ramp Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CS42L42_HSBIAS_RAMP_FAST			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CS42L42_HSBIAS_RAMP_SLOW			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CS42L42_HSBIAS_RAMP_SLOWEST			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CS42L42_HSBIAS_RAMP_TIME0			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CS42L42_HSBIAS_RAMP_TIME1			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CS42L42_HSBIAS_RAMP_TIME2			90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CS42L42_HSBIAS_RAMP_TIME3			170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* __DT_CS42L42_H */