^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_ZYNQMP_RESETS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define ZYNQMP_RESET_PCIE_CFG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ZYNQMP_RESET_PCIE_BRIDGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ZYNQMP_RESET_PCIE_CTRL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ZYNQMP_RESET_DP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ZYNQMP_RESET_SWDT_CRF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ZYNQMP_RESET_AFI_FM5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ZYNQMP_RESET_AFI_FM4 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ZYNQMP_RESET_AFI_FM3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ZYNQMP_RESET_AFI_FM2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ZYNQMP_RESET_AFI_FM1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ZYNQMP_RESET_AFI_FM0 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ZYNQMP_RESET_GDMA 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ZYNQMP_RESET_GPU_PP1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ZYNQMP_RESET_GPU_PP0 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ZYNQMP_RESET_GPU 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ZYNQMP_RESET_GT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ZYNQMP_RESET_SATA 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ZYNQMP_RESET_ACPU3_PWRON 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ZYNQMP_RESET_ACPU2_PWRON 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ZYNQMP_RESET_ACPU1_PWRON 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ZYNQMP_RESET_ACPU0_PWRON 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ZYNQMP_RESET_APU_L2 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ZYNQMP_RESET_ACPU3 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ZYNQMP_RESET_ACPU2 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ZYNQMP_RESET_ACPU1 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ZYNQMP_RESET_ACPU0 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ZYNQMP_RESET_DDR 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ZYNQMP_RESET_APM_FPD 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ZYNQMP_RESET_SOFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ZYNQMP_RESET_GEM0 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ZYNQMP_RESET_GEM1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ZYNQMP_RESET_GEM2 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ZYNQMP_RESET_GEM3 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ZYNQMP_RESET_QSPI 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ZYNQMP_RESET_UART0 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ZYNQMP_RESET_UART1 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ZYNQMP_RESET_SPI0 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ZYNQMP_RESET_SPI1 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ZYNQMP_RESET_SDIO0 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ZYNQMP_RESET_SDIO1 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ZYNQMP_RESET_CAN0 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ZYNQMP_RESET_CAN1 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ZYNQMP_RESET_I2C0 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ZYNQMP_RESET_I2C1 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ZYNQMP_RESET_TTC0 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ZYNQMP_RESET_TTC1 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ZYNQMP_RESET_TTC2 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ZYNQMP_RESET_TTC3 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ZYNQMP_RESET_SWDT_CRL 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ZYNQMP_RESET_NAND 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ZYNQMP_RESET_ADMA 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ZYNQMP_RESET_GPIO 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ZYNQMP_RESET_IOU_CC 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ZYNQMP_RESET_TIMESTAMP 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ZYNQMP_RESET_RPU_R50 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ZYNQMP_RESET_RPU_R51 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ZYNQMP_RESET_RPU_AMBA 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ZYNQMP_RESET_OCM 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ZYNQMP_RESET_RPU_PGE 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ZYNQMP_RESET_USB0_CORERESET 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ZYNQMP_RESET_USB1_CORERESET 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ZYNQMP_RESET_USB0_HIBERRESET 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ZYNQMP_RESET_USB1_HIBERRESET 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ZYNQMP_RESET_USB0_APB 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ZYNQMP_RESET_USB1_APB 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ZYNQMP_RESET_IPI 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ZYNQMP_RESET_APM_LPD 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ZYNQMP_RESET_RTC 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ZYNQMP_RESET_SYSMON 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ZYNQMP_RESET_AFI_FM6 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ZYNQMP_RESET_LPD_SWDT 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ZYNQMP_RESET_FPD 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ZYNQMP_RESET_RPU_DBG1 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ZYNQMP_RESET_RPU_DBG0 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ZYNQMP_RESET_DBG_LPD 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ZYNQMP_RESET_DBG_FPD 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ZYNQMP_RESET_APLL 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ZYNQMP_RESET_DPLL 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ZYNQMP_RESET_VPLL 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ZYNQMP_RESET_IOPLL 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ZYNQMP_RESET_RPLL 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ZYNQMP_RESET_GPO3_PL_0 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ZYNQMP_RESET_GPO3_PL_1 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ZYNQMP_RESET_GPO3_PL_2 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ZYNQMP_RESET_GPO3_PL_3 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ZYNQMP_RESET_GPO3_PL_4 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ZYNQMP_RESET_GPO3_PL_5 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ZYNQMP_RESET_GPO3_PL_6 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ZYNQMP_RESET_GPO3_PL_7 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ZYNQMP_RESET_GPO3_PL_8 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ZYNQMP_RESET_GPO3_PL_9 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ZYNQMP_RESET_GPO3_PL_10 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ZYNQMP_RESET_GPO3_PL_11 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ZYNQMP_RESET_GPO3_PL_12 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ZYNQMP_RESET_GPO3_PL_13 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ZYNQMP_RESET_GPO3_PL_14 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ZYNQMP_RESET_GPO3_PL_15 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ZYNQMP_RESET_GPO3_PL_16 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ZYNQMP_RESET_GPO3_PL_17 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ZYNQMP_RESET_GPO3_PL_18 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ZYNQMP_RESET_GPO3_PL_19 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ZYNQMP_RESET_GPO3_PL_20 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ZYNQMP_RESET_GPO3_PL_21 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ZYNQMP_RESET_GPO3_PL_22 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ZYNQMP_RESET_GPO3_PL_23 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ZYNQMP_RESET_GPO3_PL_24 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ZYNQMP_RESET_GPO3_PL_25 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ZYNQMP_RESET_GPO3_PL_26 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ZYNQMP_RESET_GPO3_PL_27 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ZYNQMP_RESET_GPO3_PL_28 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ZYNQMP_RESET_GPO3_PL_29 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ZYNQMP_RESET_GPO3_PL_30 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ZYNQMP_RESET_GPO3_PL_31 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ZYNQMP_RESET_RPU_LS 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ZYNQMP_RESET_PS_ONLY 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ZYNQMP_RESET_PL 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ZYNQMP_RESET_PS_PL0 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ZYNQMP_RESET_PS_PL1 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ZYNQMP_RESET_PS_PL2 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ZYNQMP_RESET_PS_PL3 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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