^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_VERSAL_RESETS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_VERSAL_RESETS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define VERSAL_RST_PMC_POR (0xc30c001U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define VERSAL_RST_PMC (0xc410002U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define VERSAL_RST_PS_POR (0xc30c003U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define VERSAL_RST_PL_POR (0xc30c004U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define VERSAL_RST_NOC_POR (0xc30c005U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define VERSAL_RST_FPD_POR (0xc30c006U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define VERSAL_RST_ACPU_0_POR (0xc30c007U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define VERSAL_RST_ACPU_1_POR (0xc30c008U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define VERSAL_RST_OCM2_POR (0xc30c009U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define VERSAL_RST_PS_SRST (0xc41000aU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define VERSAL_RST_PL_SRST (0xc41000bU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define VERSAL_RST_NOC (0xc41000cU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define VERSAL_RST_NPI (0xc41000dU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VERSAL_RST_SYS_RST_1 (0xc41000eU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VERSAL_RST_SYS_RST_2 (0xc41000fU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VERSAL_RST_SYS_RST_3 (0xc410010U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VERSAL_RST_FPD (0xc410011U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VERSAL_RST_PL0 (0xc410012U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define VERSAL_RST_PL1 (0xc410013U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VERSAL_RST_PL2 (0xc410014U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VERSAL_RST_PL3 (0xc410015U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VERSAL_RST_APU (0xc410016U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VERSAL_RST_ACPU_0 (0xc410017U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VERSAL_RST_ACPU_1 (0xc410018U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VERSAL_RST_ACPU_L2 (0xc410019U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VERSAL_RST_ACPU_GIC (0xc41001aU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VERSAL_RST_RPU_ISLAND (0xc41001bU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VERSAL_RST_RPU_AMBA (0xc41001cU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VERSAL_RST_R5_0 (0xc41001dU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VERSAL_RST_R5_1 (0xc41001eU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VERSAL_RST_SYSMON_LPD (0xc410023U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VERSAL_RST_PDMA_RST1 (0xc410024U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VERSAL_RST_PDMA_RST0 (0xc410025U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VERSAL_RST_ADMA (0xc410026U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VERSAL_RST_TIMESTAMP (0xc410027U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VERSAL_RST_OCM (0xc410028U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VERSAL_RST_OCM2_RST (0xc410029U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VERSAL_RST_IPI (0xc41002aU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VERSAL_RST_SBI (0xc41002bU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VERSAL_RST_LPD (0xc41002cU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VERSAL_RST_QSPI (0xc10402dU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VERSAL_RST_OSPI (0xc10402eU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VERSAL_RST_SDIO_0 (0xc10402fU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define VERSAL_RST_SDIO_1 (0xc104030U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VERSAL_RST_I2C_PMC (0xc104031U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VERSAL_RST_GPIO_PMC (0xc104032U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VERSAL_RST_GEM_0 (0xc104033U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VERSAL_RST_GEM_1 (0xc104034U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VERSAL_RST_SPARE (0xc104035U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VERSAL_RST_USB_0 (0xc104036U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define VERSAL_RST_UART_0 (0xc104037U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VERSAL_RST_UART_1 (0xc104038U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VERSAL_RST_SPI_0 (0xc104039U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VERSAL_RST_SPI_1 (0xc10403aU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VERSAL_RST_CAN_FD_0 (0xc10403bU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VERSAL_RST_CAN_FD_1 (0xc10403cU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VERSAL_RST_I2C_0 (0xc10403dU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VERSAL_RST_I2C_1 (0xc10403eU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VERSAL_RST_GPIO_LPD (0xc10403fU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define VERSAL_RST_TTC_0 (0xc104040U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VERSAL_RST_TTC_1 (0xc104041U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VERSAL_RST_TTC_2 (0xc104042U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VERSAL_RST_TTC_3 (0xc104043U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define VERSAL_RST_SWDT_FPD (0xc104044U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define VERSAL_RST_SWDT_LPD (0xc104045U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define VERSAL_RST_USB (0xc104046U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VERSAL_RST_DPC (0xc208047U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VERSAL_RST_PMCDBG (0xc208048U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VERSAL_RST_DBG_TRACE (0xc208049U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VERSAL_RST_DBG_FPD (0xc20804aU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VERSAL_RST_DBG_TSTMP (0xc20804bU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define VERSAL_RST_RPU0_DBG (0xc20804cU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define VERSAL_RST_RPU1_DBG (0xc20804dU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define VERSAL_RST_HSDP (0xc20804eU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define VERSAL_RST_DBG_LPD (0xc20804fU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define VERSAL_RST_CPM_POR (0xc30c050U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define VERSAL_RST_CPM (0xc410051U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define VERSAL_RST_CPMDBG (0xc208052U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VERSAL_RST_PCIE_CFG (0xc410053U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define VERSAL_RST_PCIE_CORE0 (0xc410054U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define VERSAL_RST_PCIE_CORE1 (0xc410055U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define VERSAL_RST_PCIE_DMA (0xc410056U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define VERSAL_RST_CMN (0xc410057U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define VERSAL_RST_L2_0 (0xc410058U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define VERSAL_RST_L2_1 (0xc410059U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define VERSAL_RST_ADDR_REMAP (0xc41005aU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define VERSAL_RST_CPI0 (0xc41005bU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define VERSAL_RST_CPI1 (0xc41005cU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define VERSAL_RST_XRAM (0xc30c05dU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define VERSAL_RST_AIE_ARRAY (0xc10405eU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define VERSAL_RST_AIE_SHIM (0xc10405fU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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