^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef __ABI_MACH_T194_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define __ABI_MACH_T194_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define TEGRA194_RESET_ACTMON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define TEGRA194_RESET_ADSP_ALL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define TEGRA194_RESET_AFI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define TEGRA194_RESET_CAN1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define TEGRA194_RESET_CAN2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TEGRA194_RESET_DLA0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TEGRA194_RESET_DLA1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEGRA194_RESET_DPAUX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA194_RESET_DPAUX1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA194_RESET_DPAUX2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA194_RESET_DPAUX3 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA194_RESET_EQOS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA194_RESET_GPCDMA 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA194_RESET_GPU 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA194_RESET_HDA 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA194_RESET_HDA2CODEC_2X 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA194_RESET_HDA2HDMICODEC 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA194_RESET_HOST1X 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA194_RESET_I2C1 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA194_RESET_I2C10 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA194_RESET_RSVD_26 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA194_RESET_RSVD_27 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA194_RESET_RSVD_28 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA194_RESET_I2C2 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA194_RESET_I2C3 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA194_RESET_I2C4 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA194_RESET_I2C6 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA194_RESET_I2C7 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA194_RESET_I2C8 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA194_RESET_I2C9 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA194_RESET_ISP 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA194_RESET_MIPI_CAL 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA194_RESET_MPHY_CLK_CTL 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA194_RESET_MPHY_L0_RX 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA194_RESET_MPHY_L0_TX 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA194_RESET_MPHY_L1_RX 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA194_RESET_MPHY_L1_TX 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA194_RESET_NVCSI 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA194_RESET_NVDEC 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA194_RESET_NVDISPLAY0_HEAD0 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA194_RESET_NVDISPLAY0_HEAD1 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA194_RESET_NVDISPLAY0_HEAD2 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEGRA194_RESET_NVDISPLAY0_HEAD3 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TEGRA194_RESET_NVDISPLAY0_MISC 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TEGRA194_RESET_NVDISPLAY0_WGRP0 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA194_RESET_NVDISPLAY0_WGRP1 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA194_RESET_NVDISPLAY0_WGRP2 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEGRA194_RESET_NVDISPLAY0_WGRP3 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA194_RESET_NVDISPLAY0_WGRP4 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TEGRA194_RESET_NVDISPLAY0_WGRP5 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TEGRA194_RESET_RSVD_56 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TEGRA194_RESET_RSVD_57 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TEGRA194_RESET_RSVD_58 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TEGRA194_RESET_NVENC 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEGRA194_RESET_NVENC1 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEGRA194_RESET_NVJPG 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TEGRA194_RESET_PCIE 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA194_RESET_PCIEXCLK 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEGRA194_RESET_RSVD_64 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TEGRA194_RESET_RSVD_65 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA194_RESET_PVA0_ALL 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEGRA194_RESET_PVA1_ALL 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA194_RESET_PWM1 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA194_RESET_PWM2 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TEGRA194_RESET_PWM3 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TEGRA194_RESET_PWM4 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEGRA194_RESET_PWM5 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TEGRA194_RESET_PWM6 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TEGRA194_RESET_PWM7 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TEGRA194_RESET_PWM8 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TEGRA194_RESET_QSPI0 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TEGRA194_RESET_QSPI1 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TEGRA194_RESET_SATA 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TEGRA194_RESET_SATACOLD 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TEGRA194_RESET_SCE_ALL 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TEGRA194_RESET_RCE_ALL 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TEGRA194_RESET_SDMMC1 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TEGRA194_RESET_RSVD_83 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TEGRA194_RESET_SDMMC3 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TEGRA194_RESET_SDMMC4 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TEGRA194_RESET_SE 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TEGRA194_RESET_SOR0 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TEGRA194_RESET_SOR1 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TEGRA194_RESET_SOR2 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TEGRA194_RESET_SOR3 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TEGRA194_RESET_SPI1 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TEGRA194_RESET_SPI2 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TEGRA194_RESET_SPI3 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TEGRA194_RESET_SPI4 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TEGRA194_RESET_TACH 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TEGRA194_RESET_RSVD_96 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TEGRA194_RESET_TSCTNVI 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TEGRA194_RESET_TSEC 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEGRA194_RESET_TSECB 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TEGRA194_RESET_UARTA 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TEGRA194_RESET_UARTB 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA194_RESET_UARTC 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TEGRA194_RESET_UARTD 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TEGRA194_RESET_UARTE 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEGRA194_RESET_UARTF 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA194_RESET_UARTG 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA194_RESET_UARTH 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA194_RESET_UFSHC 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA194_RESET_UFSHC_AXI_M 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA194_RESET_UFSHC_LP_SEQ 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA194_RESET_RSVD_111 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TEGRA194_RESET_VI 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA194_RESET_VIC 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TEGRA194_RESET_XUSB_PADCTL 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TEGRA194_RESET_NVDEC1 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TEGRA194_RESET_PEX0_CORE_0 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TEGRA194_RESET_PEX0_CORE_1 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TEGRA194_RESET_PEX0_CORE_2 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TEGRA194_RESET_PEX0_CORE_3 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TEGRA194_RESET_PEX0_CORE_4 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA194_RESET_PEX0_CORE_0_APB 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA194_RESET_PEX0_CORE_1_APB 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA194_RESET_PEX0_CORE_2_APB 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA194_RESET_PEX0_CORE_3_APB 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA194_RESET_PEX0_CORE_4_APB 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA194_RESET_PEX0_COMMON_APB 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA194_RESET_PEX1_CORE_5 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA194_RESET_PEX1_CORE_5_APB 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA194_RESET_CVNAS 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA194_RESET_CVNAS_FCM 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TEGRA194_RESET_DMIC5 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TEGRA194_RESET_APE 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA194_RESET_PEX_USB_UPHY 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TEGRA194_RESET_PEX_USB_UPHY_L0 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEGRA194_RESET_PEX_USB_UPHY_L1 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEGRA194_RESET_PEX_USB_UPHY_L2 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TEGRA194_RESET_PEX_USB_UPHY_L3 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA194_RESET_PEX_USB_UPHY_L4 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEGRA194_RESET_PEX_USB_UPHY_L5 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TEGRA194_RESET_PEX_USB_UPHY_L6 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TEGRA194_RESET_PEX_USB_UPHY_L7 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TEGRA194_RESET_PEX_USB_UPHY_L8 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TEGRA194_RESET_PEX_USB_UPHY_L9 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TEGRA194_RESET_PEX_USB_UPHY_L10 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA194_RESET_PEX_USB_UPHY_L11 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TEGRA194_RESET_PEX_USB_UPHY_PLL0 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA194_RESET_PEX_USB_UPHY_PLL1 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TEGRA194_RESET_PEX_USB_UPHY_PLL2 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TEGRA194_RESET_PEX_USB_UPHY_PLL3 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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