Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _ABI_MACH_T186_RESET_T186_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _ABI_MACH_T186_RESET_T186_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define TEGRA186_RESET_ACTMON			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define TEGRA186_RESET_AFI			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define TEGRA186_RESET_CEC			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define TEGRA186_RESET_CSITE			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define TEGRA186_RESET_DP2			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define TEGRA186_RESET_DPAUX			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define TEGRA186_RESET_DSI			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define TEGRA186_RESET_DSIB			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define TEGRA186_RESET_DTV			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define TEGRA186_RESET_DVFS			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define TEGRA186_RESET_ENTROPY			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define TEGRA186_RESET_EXTPERIPH1		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define TEGRA186_RESET_EXTPERIPH2		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define TEGRA186_RESET_EXTPERIPH3		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TEGRA186_RESET_GPU			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TEGRA186_RESET_HDA			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TEGRA186_RESET_HDA2CODEC_2X		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TEGRA186_RESET_HDA2HDMICODEC		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TEGRA186_RESET_HOST1X			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TEGRA186_RESET_I2C1			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TEGRA186_RESET_I2C2			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TEGRA186_RESET_I2C3			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TEGRA186_RESET_I2C4			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TEGRA186_RESET_I2C5			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TEGRA186_RESET_I2C6			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TEGRA186_RESET_ISP			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TEGRA186_RESET_KFUSE			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TEGRA186_RESET_LA			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TEGRA186_RESET_MIPI_CAL			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TEGRA186_RESET_PCIE			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TEGRA186_RESET_PCIEXCLK			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TEGRA186_RESET_SATA			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TEGRA186_RESET_SATACOLD			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TEGRA186_RESET_SDMMC1			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TEGRA186_RESET_SDMMC2			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TEGRA186_RESET_SDMMC3			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TEGRA186_RESET_SDMMC4			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TEGRA186_RESET_SE			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TEGRA186_RESET_SOC_THERM		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TEGRA186_RESET_SOR0			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TEGRA186_RESET_SPI1			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TEGRA186_RESET_SPI2			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define TEGRA186_RESET_SPI3			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define TEGRA186_RESET_SPI4			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define TEGRA186_RESET_TMR			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TEGRA186_RESET_TRIG_SYS			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define TEGRA186_RESET_TSEC			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TEGRA186_RESET_UARTA			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define TEGRA186_RESET_UARTB			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define TEGRA186_RESET_UARTC			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define TEGRA186_RESET_UARTD			50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define TEGRA186_RESET_VI			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define TEGRA186_RESET_VIC			52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define TEGRA186_RESET_XUSB_DEV			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define TEGRA186_RESET_XUSB_HOST		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define TEGRA186_RESET_XUSB_PADCTL		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define TEGRA186_RESET_XUSB_SS			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define TEGRA186_RESET_AON_APB			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define TEGRA186_RESET_AXI_CBB			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define TEGRA186_RESET_BPMP_APB			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define TEGRA186_RESET_CAN1			60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define TEGRA186_RESET_CAN2			61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define TEGRA186_RESET_DMIC5			62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define TEGRA186_RESET_DSIC			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define TEGRA186_RESET_DSID			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define TEGRA186_RESET_EMC_EMC			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define TEGRA186_RESET_EMC_MEM			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define TEGRA186_RESET_EMCSB_EMC		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define TEGRA186_RESET_EMCSB_MEM		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define TEGRA186_RESET_EQOS			69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define TEGRA186_RESET_GPCDMA			70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define TEGRA186_RESET_GPIO_CTL0		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define TEGRA186_RESET_GPIO_CTL1		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define TEGRA186_RESET_GPIO_CTL2		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define TEGRA186_RESET_GPIO_CTL3		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define TEGRA186_RESET_GPIO_CTL4		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define TEGRA186_RESET_GPIO_CTL5		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define TEGRA186_RESET_I2C10			77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define TEGRA186_RESET_I2C12			78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define TEGRA186_RESET_I2C13			79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define TEGRA186_RESET_I2C14			80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define TEGRA186_RESET_I2C7			81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TEGRA186_RESET_I2C8			82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TEGRA186_RESET_I2C9			83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define TEGRA186_RESET_JTAG2AXI			84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define TEGRA186_RESET_MPHY_IOBIST		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define TEGRA186_RESET_MPHY_L0_RX		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define TEGRA186_RESET_MPHY_L0_TX		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define TEGRA186_RESET_NVCSI			88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define TEGRA186_RESET_NVDISPLAY0_HEAD0		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEGRA186_RESET_NVDISPLAY0_HEAD1		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TEGRA186_RESET_NVDISPLAY0_HEAD2		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TEGRA186_RESET_NVDISPLAY0_MISC		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA186_RESET_NVDISPLAY0_WGRP0		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TEGRA186_RESET_NVDISPLAY0_WGRP1		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TEGRA186_RESET_NVDISPLAY0_WGRP2		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEGRA186_RESET_NVDISPLAY0_WGRP3		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA186_RESET_NVDISPLAY0_WGRP4		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA186_RESET_NVDISPLAY0_WGRP5		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA186_RESET_PWM1			99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA186_RESET_PWM2			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA186_RESET_PWM3			101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA186_RESET_PWM4			102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TEGRA186_RESET_PWM5			103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA186_RESET_PWM6			104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TEGRA186_RESET_PWM7			105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TEGRA186_RESET_PWM8			106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TEGRA186_RESET_SCE_APB			107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TEGRA186_RESET_SOR1			108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TEGRA186_RESET_TACH			109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TEGRA186_RESET_TSC			110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TEGRA186_RESET_UARTF			111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA186_RESET_UARTG			112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA186_RESET_UFSHC			113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA186_RESET_UFSHC_AXI_M		114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA186_RESET_UPHY			115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA186_RESET_ADSP			116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA186_RESET_ADSPDBG			117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA186_RESET_ADSPINTF			118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA186_RESET_ADSPNEON			119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA186_RESET_ADSPPERIPH		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA186_RESET_ADSPSCU			121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TEGRA186_RESET_ADSPWDT			122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TEGRA186_RESET_APE			123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA186_RESET_DPAUX1			124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TEGRA186_RESET_NVDEC			125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEGRA186_RESET_NVENC			126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEGRA186_RESET_NVJPG			127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TEGRA186_RESET_PEX_USB_UPHY		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA186_RESET_QSPI			129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEGRA186_RESET_TSECB			130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TEGRA186_RESET_VI_I2C			131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TEGRA186_RESET_UARTE			132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TEGRA186_RESET_TOP_GTE			133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TEGRA186_RESET_SHSP			134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TEGRA186_RESET_PEX_USB_UPHY_L5		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA186_RESET_PEX_USB_UPHY_L4		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TEGRA186_RESET_PEX_USB_UPHY_L3		137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA186_RESET_PEX_USB_UPHY_L2		138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TEGRA186_RESET_PEX_USB_UPHY_L1		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TEGRA186_RESET_PEX_USB_UPHY_L0		140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TEGRA186_RESET_PEX_USB_UPHY_PLL1	141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA186_RESET_PEX_USB_UPHY_PLL0	142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TEGRA186_RESET_TSCTNVI			143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TEGRA186_RESET_EXTPERIPH4		144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TEGRA186_RESET_DSIPADCTL		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TEGRA186_RESET_AUD_MCLK			146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TEGRA186_RESET_MPHY_CLK_CTL		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TEGRA186_RESET_MPHY_L1_RX		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TEGRA186_RESET_MPHY_L1_TX		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TEGRA186_RESET_UFSHC_LP			150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TEGRA186_RESET_BPMP_NIC			151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TEGRA186_RESET_BPMP_NSYSPORESET		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TEGRA186_RESET_BPMP_NRESET		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TEGRA186_RESET_BPMP_DBGRESETN		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TEGRA186_RESET_BPMP_PRESETDBGN		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TEGRA186_RESET_BPMP_PM			156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TEGRA186_RESET_BPMP_CVC			157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TEGRA186_RESET_BPMP_DMA			158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TEGRA186_RESET_BPMP_HSP			159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TEGRA186_RESET_TSCTNBPMP		160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TEGRA186_RESET_BPMP_TKE			161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TEGRA186_RESET_BPMP_GTE			162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TEGRA186_RESET_BPMP_PM_ACTMON		163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TEGRA186_RESET_AON_NIC			164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TEGRA186_RESET_AON_NSYSPORESET		165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TEGRA186_RESET_AON_NRESET		166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TEGRA186_RESET_AON_DBGRESETN		167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TEGRA186_RESET_AON_PRESETDBGN		168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TEGRA186_RESET_AON_ACTMON		169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TEGRA186_RESET_AOPM			170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TEGRA186_RESET_AOVC			171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TEGRA186_RESET_AON_DMA			172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TEGRA186_RESET_AON_GPIO			173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TEGRA186_RESET_AON_HSP			174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TEGRA186_RESET_TSCTNAON			175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TEGRA186_RESET_AON_TKE			176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TEGRA186_RESET_AON_GTE			177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TEGRA186_RESET_SCE_NIC			178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TEGRA186_RESET_SCE_NSYSPORESET		179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TEGRA186_RESET_SCE_NRESET		180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TEGRA186_RESET_SCE_DBGRESETN		181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TEGRA186_RESET_SCE_PRESETDBGN		182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TEGRA186_RESET_SCE_ACTMON		183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TEGRA186_RESET_SCE_PM			184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TEGRA186_RESET_SCE_DMA			185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TEGRA186_RESET_SCE_HSP			186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TEGRA186_RESET_TSCTNSCE			187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TEGRA186_RESET_SCE_TKE			188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TEGRA186_RESET_SCE_GTE			189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TEGRA186_RESET_SCE_CFG			190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TEGRA186_RESET_ADSP_ALL			191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TEGRA186_RESET_UFSHC_LP_SEQ		192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TEGRA186_RESET_SIZE			193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #endif