^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This header provides Tegra124-specific constants for binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * nvidia,tegra124-car.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_RESET_TEGRA124_CAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define TEGRA124_RESET(x) (6 * 32 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */